SPI help

[dietert1]

In the BT817 datasheet "4.1.1 QSPI Interface" it says the SPI only operates in mode 0. Then you can go to:
https://en.wikipedia.org/wiki/Serial_Peripheral_Interface
and see the timing diagram and the relationship of CPOL and CPHASE to the SPI mode index. Then you know the correct configuration of the SPI master.
The ADUC SPI is limited at 20 MHz while the BT817 spec is 30 MHz.
The ethernet chip SPI timing is in datasheet figures 6-9 and 6-10. There is a complication with "low speed" and "fast speed" setup. And the SPI pins also serve other functions. Maybe a bit tricky to get it all working properly.

Regards, Dieter

Edit: The ADUC has two SPI issues in its errata ("Silicon Anomaly"). er007 affects slave mode, er004 restricts bit rate. Other info: https://ez.analog.com/microcontrollers/arm7-core-products/f/q-a/18321/has-anybody-got-example-code-that-maximizes-the-spi-baud-rate-in-master-slave-mode (remark about weak SPI clock).

[Postal2]

... which is why your posts usually make a bit of sense but are of no use to anybody working on something specific.

You are right. I see.

[Northy]

Well now I feel like a total fool, the timing was there all along. 
Sorry guys.

G

[Siwastaja]

What a weird and obsolete microcontroller, but that does not matter, took 2 minutes to find the datasheet and SPI configuration register:

https://www.analog.com/media/en/technical-documentation/data-sheets/aduc7023.pdf
page 59

3 SPICPO Serial clock polarity mode bit.
This bit is set by the user; the serial clock idles high.
This bit is cleared by the user; the serial clock idles low.
2 SPICPH Serial clock phase mode bit.
This bit is set by the user; the serial clock pulses at the beginning of each serial bit transfer.
This bit is cleared by the user; the serial clock pulses at the end of each serial bit transfe

Now try out the four choices (00, 01, 10 and 11). Well three left because you already have one (non-working) in use.

[Postal2]

There is one small problem. Assuming that there is no resonance, connecting the oscilloscope probe will shift CLK forward, as will the 10 pF capacitor. Let's assume that the polarity of CLK is reversed. Then any forward shift of CLK should make the situation worse. However, connecting the probe normalizes the situation. For the wrong polarity, this means that CLK moves backward. The author has invented a Time Machine.

[peter-h]

What a weird and obsolete microcontroller

I thought that too. It is 15 years old. I suspect the OP is not the designer in this case; probably was handed this to do an add-on. Nobody would choose a chip like this and especially not from that company

It's not a crazy-expensive chip though, looking at Mouser etc.

[Northy]

Hi all,

I'm feeling a bit better today.
I'll try the other modes tomorrow, but today I used the logic analyser to confirm that the SPI is as per the requirements of both IC data sheets.
I'll look at the physical integrity of the waveforms tomorrow, but I'm back to struggling to measure it with the scope that I've got.

Thanks for your help so far.

G

[Northy]

Hi all,

Thank you for your help with all this, it is much appreciated.
I have made the design reliable (it seems) with a 49R resistor in the CLK line.

I watched this video last night:


In the video the guy states that you should consider a Pi filter for cables between boards. If I was add these for the FCC cable link is there an resource anywhere to show how you should design it?

Thanks,

G

[Postal2]

... I have made the design reliable (it seems) with a 49R resistor in the CLK line. ....

Well done.

.... a Pi filter for cables between boards. ...

Your frequency is 5 MHz. Up to 10 MHz you only need to worry about ringing on the CLK line, if it concerns the reliability of your device and there are no requirements for interference from your device.

[peter-h]

I have made the design reliable (it seems) with a 49R resistor in the CLK line.

Possibky only by luck. You need to verify the timing properly.

Your frequency is 5 MHz. Up to 10 MHz you only need to worry about ringing on the CLK line

Nonsense; ringing is related to the edge properties, not the clock frequency.

[Siwastaja]

It could be false clock edges due to massive amount of ringing but I'm still not convinced. Series resistor will add a tiny bit of delay so it could be still wrong clock polarity, just like adding scope probe adds delay, adding series R adds delay too. But SPI should not be sensitive to tiny changes in delay. So I would still remove the resistor (or add 10pF, or whatever you did to make it inoperational) and do what we have been suggesting from the start, try different clock configuration. A tiny change in code which takes less time to test than soldering any resistors.

Adding series termination to clock line only makes no sense, once you are at it, add 49R to all other outputs as well (so MOSI and nCS at master site; MISO at slave site). If we then hear about problem coming back... 

Still no layout pictures and/or photos. (Bonus points for schematics.)

Finally, after you are sure that clock configuration is correct and figured out why you had problems, then adding series termination (that 49R) is definitely correct thing to do so doesn't hurt, but before going for more filtering please identify if you have a problem, then find the reason for the problem, and only then add a filter designed to correct the problem if it can't be solved otherwise (e.g. better layout).

[Postal2]

Possibky only by luck. ...

I guess when you do something, it's just luck that helps you.

[dietert1]

You can certainly find many youtube videos with engineers unaware of SPI modes, who try to save their wrong designs by some extra resistors. A correct SPI transfer doesn't need those resistors nor any other termination. If it makes a difference, setup/hold times are marginal i.e. the digital design is inconsistent.

Regards, Dieter

Edit: According to the AD forum post i linked above the ADUC SPI clock output is weak and won't produce ringing.

[Postal2]

.... According to the AD forum post i linked above ....

It's called a "relay race", you asked on one forum, dragged it here, someone will drag it to a third... It's a common thing.

[Siwastaja]

A correct SPI transfer doesn't need those resistors nor any other termination.

Well, to be fair, need of termination is an "analog" issue in the sense that protocol does not matter. You need termination if the slew rate of the driver is high enough and the trace you are driving is long enough for transmission line effects to be relevant.

Slew rates vary between different microcontroller families, and some also have configurable drive strengths.

For a PCB trace a few centimeters long, termination rarely makes any difference, but here the combined length of traces and cable are long enough that termination might be well necessary to pass EMC.

Good SI is always worth investigating some time into and series termination resistors cheap, but I agree with you that it's not likely the reason for the functional issues OP is seeing.

[dietert1]

.... According to the AD forum post i linked above ....

It's called a "relay race", you asked on one forum, dragged it here, someone will drag it to a third... It's a common thing.

That was an official contribution from an AD employee, labeled "ADApproved". Don't try to confuse people. You aren't the one who knows better.

[Postal2]

... Don't try to confuse people. ...

If anyone is confusing people, it's you and your company. If you hadn't posted your nonsense about the configuration, the author would have solved everything in 1 day.

[Siwastaja]

Just try the three other configurations.

[ebastler]

Just try the three other configurations.

Kudos for repeating that calmly and without resorting to exclamation marks or emojis.

[Siwastaja]

But it's quite interesting to see that while everybody else deals with SPI clocking issues by choosing the correct clocking configuration, there is at least one who has never heard about SPI clocking modes and uses carefully tuned series inductors and parallel capacitors on the clock line to tune the delay to achieve a "working" system, and probably has had some success doing that.

I guess, if all you have is a hammer, ...

[Postal2]

...  while everybody else deals with SPI clocking issues by choosing the correct clocking configuration, ...

Based on the symptoms described by the author, even a monkey can understand what is going on.

[Northy]

Guys, I'm sorry if you are upset with me, it's not what I wanted.

I have used a logic analyser to confirm that the timing is correct as per the detailed timing diagrams from the data sheets that I'd missed.

I had a look around with the scope today and there was a lot of ringing. So I added the 49R9 to the clk line as a quick test as it had been suggested that was the most important trace. Yes, I should add them to all, but it's particularly fiddly to do. I'll look at it tomorrow.

I've already made a list of things that can be done better on the next iteration of the layout.

I can try the other SPI modes. Both ICs require mode 0, I've verified that the mode is set to 0, and checked the timing is correct to the datasheets, but I'll try the other modes too.

At 5MHz do I not need any filtering either side of the FFC cable?

Thanks,

G

[ebastler]

Guys, I'm sorry if you are upset with me, it's not what I wanted.

I can't speak for Siwastaja and dietert1, but as far as I am concerned, don't worry, I am not upset with you. 

[Postal2]

.... So I added the 49R9 to the clk line as a quick test as it had been suggested that was the most important trace. Yes, I should add them to all, but it's particularly fiddly to do. ....

If you have a requirement for interference from your device, then you will have to install resistors on all lines. If you are only concerned about reliability, then installing additional resistors will not affect anything. The fact is that ringing occurs only on the signal fronts, it will have time to fade before the time of strobing.

....  At 5MHz do I not need any filtering either side of the FFC cable?

If you install resistors on all lines, then no filters are needed. Filtering is needed again because of interference. For reliability, you only need one resistor, which you have already installed.

[Siwastaja]

Guys, I'm sorry if you are upset with me, it's not what I wanted.

Post the information we are asking and we won't be upset . (No, really, I'm having a good time with this thread, mostly thanks to Postal2.)

I mean the low hanging fruit stuff which takes less than a minute for you to produce. Screenshot of schematic, layout, maybe a photograph of the device. It's not like you have to take it using a film camera, develop the film and scan the pictures.

I have used a logic analyser to confirm that the timing is correct as per the detailed timing diagrams from the data sheets that I'd missed.

That would be easier to verify if you posted a screen capture or photograph of the logic analyzer screen.

I had a look around with the scope today and there was a lot of ringing. So I added the 49R9 to the clk line as a quick test as it had been suggested that was the most important trace. Yes, I should add them to all, but it's particularly fiddly to do. I'll look at it tomorrow.

Very excessive ringing can cause issues like this, so it's a real possibility. Definitely add the resistors to the rest of the traces as well. At the driver; so MISO would be at the slave, others at master.

Seeing the scope image would be interesting. Some ringing which actually is not there will also result in from the loop of the ground clip, so if you still have the little metal springy thing which came with the oscilloscope probe (it is easy to lose it), use that. Scratch some solder mask off from the ground plane so you can touch the spring thing, and probe the signal.

And oh, always probe at the receiver pin. Especially now as you have the series termination resistor in place; by definition of source termination signal is only valid at the receiving end of the transmission line.

At 5MHz do I not need any filtering either side of the FFC cable?

5MHz is the data rate and does not mean much else except maybe giving an ultimate limit to how much you can allow your filter to slow down the signal.

Filtering has two different purposes, to reduce emissions and/or to increase immunity. But you should definitely start by fixing the layout (including your cable signal arrangement) because if it's proper then you should not be having emission/immunity problem in the first place. After proper layout, terminate the signals with the source series resistor and it's very unlikely you need any extra filtration. Well increasing the series resistance value beyond the exact characteristic impedance of the trace already is filtering.