Spikes in Diodes AP63205 switching supply design

[Misieek]

Hi everyone,

I’m facing an issue with a 5V voltage regulator I designed using the AP63205 switching regulator to power an ESP32 C3 supermini module. The problem is that the ADC readings on the ESP32 are very unstable. I measured the 5V output voltage with an oscilloscope and noticed significant spikes, which seem to be the root cause of the issue.

To investigate, I ran some tests under different conditions:

>Without any load (infinite resistance) using DC coupling (see: OnlyAP63205_InfOhmLoad_DC1 and DC2).
>With a 60Ω resistor load using DC coupling (OnlyAP63205_60ohmLoad_DC).
>With AC coupling for both infinite resistance (OnlyAP63205_InfOhmLoad_AC) and 60Ω load (OnlyAP63205_60ohmLoad_AC).

Next, I added a 390μF low-ESR capacitor at the output (paralel to C6) and measured again with a 60Ω load (OnlyAP63205_60ohmLoad_AC_390uF_LOWESRatOutput). This significantly reduced the spikes, but they are still present, and I don’t know what’s causing them or how to eliminate them completely.

Finally, I tested the circuit with the ESP32 module soldered in and observed the output (AP63205_ESP32Load_AC_390uF_LOWESRatOutput).

I’ve attached the schematic, board layout, and oscilloscope screenshots for reference. I’d really appreciate your insights on what could be causing these voltage spikes?

Thanks in advance for your help!

[Konkedout]

I do not see either your schematic diagram or your pcb layout.  Also please provide a link to the device datasheet  BEWARE:

1) Good pcb layout is critical to minimize output spikes.

2) Proper probing technique also.  Do not use a ground clip lead on your oscilloscope probe.  Use a coil of bare wire to ground the probe shield at the output filter capacitor.

3) Include 1 or more chip ceramic capacitors in the output for low ESR/Low ESL ripple filtering.  Again...proper layout.  You can also include bulk filtering such as tantalum or aluminum electrolytic.

[Misieek]

Yes, I'm sorry. I thought that i posted the schematic and layout... but it turned out I didn't.

Also, here is the link to the AP63205 datasheet https://www.tme.eu/Document/50f40feddcdc52ad3ba5db915ce521ca/AP63200-1-3-5.pdf. I mounted 10nF and 100nF ceramic X7R as close as I could to C6 and measured voltage with the shorter probe, as advised. With the 60 resistor load, the result is as it can be seen on AP63205_60ohmLoad_390uF_100nF_10uF picture. So, the swings are +/- 60mV. 

[Konkedout]

Well right away I see big problems with your layout.

I went to the trouble of downloading the datasheet.  Look at Figure 25 layout.  You need to pay careful attention to that.

Probably the top priority is a tight bypass between Vin on pin 3 and Gnd on pin 4.  The datasheet fig 25 shows C1 input bypass capacitor positioned as close as possible between those two pins.  A buck regulator has high dI/dt in the input circuit, with high frequency current spikes flowing through the input bypass capacitor.  That is called a "hot loop."  Without a good bypass there the chip will see big voltage spikes at its input pin.

In your layout, I see what looks like a bypass capacitor Southwest of pin 1 of the chip.  I cannot easily tell how long a path the ground end has back to pin 4.  "Houston.  We have a problem"  (Spoken by Tom Hanks in the movie "Apollo 13") 

Do not try to lay out this board without a ground plane layer, at least in the area under the IC.  Maybe you have one and are not showing it, or maybe you do not have one.

This looks like it may be a KiCad file.  If you are OK with zipping and posting your project folder, go ahead and do that.  But anyway....you need to carefully follow the example of DS figure 25.

Around Y2K I tested a buck regulator board which did not work at all.  The schematic was good and the board agreed with it.  The whole problem was bad layout.

If you can solder a chip bypass capacitor RIGHT BETWEEN pins 3-4 that might help significantly.  Small size (0402 or 0603; I would not go bigger than 0805) probably 1 uF to 4.7 uF rating.  Small size for low inductance and to fit close up is more important than many uF.

I have been designing switching power supplies since about 1980....

[analityk]

One think about filtering caps against small size. Ofc smallest possbible inductance is priority but there is also self resonant frequency. While connection inductance is fixed for given capacitor size you will always select biggest capacity in this size. Then your self resonant frequency will be the highest possible. From the other side, if 1uF is sufficient for decouping then you will find one with smallest size (and proper dielectric).

[PGPG]

So, the swings are +/- 60mV. 

I have never decided for DCDC working at higher frequency than 500kHz.
All my 2 layer PCBs have 100% continuous GND at bottom layer.

When you draw the current path in both DCDC cycles at your layout you will see that good/short GND connection between input and output capacitor is one of critical factors.
At recommended layout in datasheet you see capacitors positioned with their GND pads next to each other and at your PCB GND current from one capacitor to the other have long way and even at the place you could make it little shorter by placing the via (just over the mounting hole) you didn't did it.
I am looking at DCDC layout the following way. Imagine that these two current paths shine alternately. Your task is to make the distance from which looking at PCB you will not notice blinking as short as possible. These two paths should be as similar to each other as possible. So the difference between them should be as small as possible.
Recently at KiCad forum one user who spend his live designing DCDC said that these difference between these two circuits is the main circuit you should carry about as it is the only circuit with rapid current changes. It is because in both circuits current flows there is the choke inside and choke guarantees current don't change rapidly. But it rapidly switches between these two circuits so it is really a current in the circuit being the difference of them that has the highest frequency harmonics.
I know I have practically said the same thing twice but believe it help to understand it.

I am using LM5017. To work stable it needs about 50mV (25mV minimum) ripple at its feedback pin so your 60mV doesn't shock me. I think the main reasons are impedances at PCB and in your connections of externally connected ceramic capacitors. As you have 1.1MHz while I typically have 350kHz you could expect 3 times higher pulses at the same ESL (Equivalent Serial L).
Compare ESR and ESL of electrolytic capacitors and SMD ceramic capacitors.

[Misieek]

Thanks for great advices. Can you suggest any materials to learn more about designing PCBs for switching regulators?

I soldered 2.2uF 25V and 22uF 25V ceramics between AP63205 pins. I also added some additional wire between C4 and C7 GNDs. Here is the result (AP63205_60ohmLoad_13.01).

The frequency inside swings corresponds to 1.1MHz (which would correspond to chip switching frequency), and the frequency between them occuring is somewhere around 90kHz.  I am starting to think that 60mV swing can be a normal thing with this type of regulator. However, I need more stable voltage, so how can this be achieved?

[PGPG]

I need more stable voltage, so how can this be achieved?

I have never used DCDC in my circuits without pi filters at input and at output.
In my circuit (LM5017, 350KHz, input up to 28V (surge pulses up to 50V), output 3V3 300mA) at output I use two pi stages with 1k ferryte beads (power type with small DC R) and ceramic 10uF capacitors. I use ferryte beads as they don't resonate at high frequencies because there they convert energy into heat. But I don't know if for higher current voltage drop at them will still be acceptable.

In past (20 years ago) I used sometimes Spice and I used it practically only to simulate supply filters using L and C models containing their parasitic components. Using Spice you can get feeling what will be happening with pulses you have at your output after passing it through filter.
I was using PSPICE I got in 90s demo version (limited to 30 nets). It allowed to have voltage source driven from text file with sample series. I was able to save oscilloscope output in file and use as source in Spice.

[tom66]

It is not normal to have such ripple on the output of the converter.

Typically you might expect around 10-20mV at light load.

Your oscilloscope shot suggests a long path from the output capacitor to the inductor or the ground.