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Spikes in Diodes AP63205 switching supply design
Misieek:
Hi everyone,
I’m facing an issue with a 5V voltage regulator I designed using the AP63205 switching regulator to power an ESP32 C3 supermini module. The problem is that the ADC readings on the ESP32 are very unstable. I measured the 5V output voltage with an oscilloscope and noticed significant spikes, which seem to be the root cause of the issue.
To investigate, I ran some tests under different conditions:
>Without any load (infinite resistance) using DC coupling (see: OnlyAP63205_InfOhmLoad_DC1 and DC2).
>With a 60Ω resistor load using DC coupling (OnlyAP63205_60ohmLoad_DC).
>With AC coupling for both infinite resistance (OnlyAP63205_InfOhmLoad_AC) and 60Ω load (OnlyAP63205_60ohmLoad_AC).
Next, I added a 390μF low-ESR capacitor at the output (paralel to C6) and measured again with a 60Ω load (OnlyAP63205_60ohmLoad_AC_390uF_LOWESRatOutput). This significantly reduced the spikes, but they are still present, and I don’t know what’s causing them or how to eliminate them completely.
Finally, I tested the circuit with the ESP32 module soldered in and observed the output (AP63205_ESP32Load_AC_390uF_LOWESRatOutput).
I’ve attached the schematic, board layout, and oscilloscope screenshots for reference. I’d really appreciate your insights on what could be causing these voltage spikes?
Thanks in advance for your help!
Konkedout:
I do not see either your schematic diagram or your pcb layout. Also please provide a link to the device datasheet BEWARE:
1) Good pcb layout is critical to minimize output spikes.
2) Proper probing technique also. Do not use a ground clip lead on your oscilloscope probe. Use a coil of bare wire to ground the probe shield at the output filter capacitor.
3) Include 1 or more chip ceramic capacitors in the output for low ESR/Low ESL ripple filtering. Again...proper layout. You can also include bulk filtering such as tantalum or aluminum electrolytic.
Misieek:
Yes, I'm sorry. I thought that i posted the schematic and layout... but it turned out I didn't.
Also, here is the link to the AP63205 datasheet https://www.tme.eu/Document/50f40feddcdc52ad3ba5db915ce521ca/AP63200-1-3-5.pdf. I mounted 10nF and 100nF ceramic X7R as close as I could to C6 and measured voltage with the shorter probe, as advised. With the 60 \$\Omega\$ resistor load, the result is as it can be seen on AP63205_60ohmLoad_390uF_100nF_10uF picture. So, the swings are +/- 60mV. :wtf:
Konkedout:
Well right away I see big problems with your layout.
I went to the trouble of downloading the datasheet. Look at Figure 25 layout. You need to pay careful attention to that.
Probably the top priority is a tight bypass between Vin on pin 3 and Gnd on pin 4. The datasheet fig 25 shows C1 input bypass capacitor positioned as close as possible between those two pins. A buck regulator has high dI/dt in the input circuit, with high frequency current spikes flowing through the input bypass capacitor. That is called a "hot loop." Without a good bypass there the chip will see big voltage spikes at its input pin.
In your layout, I see what looks like a bypass capacitor Southwest of pin 1 of the chip. I cannot easily tell how long a path the ground end has back to pin 4. "Houston. We have a problem" (Spoken by Tom Hanks in the movie "Apollo 13")
Do not try to lay out this board without a ground plane layer, at least in the area under the IC. Maybe you have one and are not showing it, or maybe you do not have one.
This looks like it may be a KiCad file. If you are OK with zipping and posting your project folder, go ahead and do that. But anyway....you need to carefully follow the example of DS figure 25.
Around Y2K I tested a buck regulator board which did not work at all. The schematic was good and the board agreed with it. The whole problem was bad layout.
If you can solder a chip bypass capacitor RIGHT BETWEEN pins 3-4 that might help significantly. Small size (0402 or 0603; I would not go bigger than 0805) probably 1 uF to 4.7 uF rating. Small size for low inductance and to fit close up is more important than many uF.
I have been designing switching power supplies since about 1980....
analityk:
One think about filtering caps against small size. Ofc smallest possbible inductance is priority but there is also self resonant frequency. While connection inductance is fixed for given capacitor size you will always select biggest capacity in this size. Then your self resonant frequency will be the highest possible. From the other side, if 1uF is sufficient for decouping then you will find one with smallest size (and proper dielectric).
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