I'm posting below the third version of my LTC1043-based capacitance meter.

This iteration follows recent discussions with David Hess, let me first shortly recall the background.

NB. I started working on this yesterday evening and I see now there have been new posts since, I apologize for not taking them into account yet.

As David Hess pointed out there is an issue regarding the stability of the reference capacitor (C2). I looked into this and it is not easy indeed to find relatively big (1uf) capacitors having low temperature coefficients. With 500 ppm/°C or more it would be difficult to keep the required 0.1% stability over a reasonable temperature range.

The temperature drift could in principle be compensated using a PTC /NTC combination as suggested e.g. here :

https://www.tdk-electronics.tdk.com/download/530754/480aeb04c789e45ef5bb9681513474ba/pdf-generaltechnicalinformation.pdfbut there is also a huge humidity dependence so I'm not sure it would be reliable.

On the other hand David Hess recalled that 1) voltage references are much more stable than capacitors and are cheap today, 2) integrating designs can achieve high stability. I have built on that for my new design.

There was also a suggestion of adapting a V/F converter. Now I found some time to look more closely at the V/F converter example in the LTC1043 datasheet, this circuit is analyzed in the AD application note

https://www.analog.com/media/en/technical-documentation/application-notes/an03f.pdfHowever I'm not sure it would still be good for capacitances as low as 15pF.

If I understand it correctly, it is basically a 555-like RC-discharge design albeit using precision components. But like with all RC designs the weak point is in the comparator (here the comparator is hidden in the LTC1043 clock circuitry). A comparator is a high-gain device and as such it highly amplifies noise and produces jitter (I already mentioned the jitter problem of RC based oscillators in my post of Oct 20). And we can reasonably guess that the smaller the available charge to drive the comparator inputs the bigger jitter will be (*). Finally the least frequently we have to compare anything the better the performance hence the idea of accumulating charge packets in a bigger capacitor.

(*) Here the charge is amplified by the LF356 opamp but I don't think it changes the problem fundamentally, I'm open to discussion though.

With a 10pF range capacitor even a high performance V/F converter like the one suggested in the appnotes will suffer, we either need a very high switching frequency or very large resistances and ridicously small currents. I strongly suspect that for 10pF range the performance would drop dramatically.

For these reasons I stick to the idea of accumulating charge packets in a bigger capacitor.

Now the problem is the big capacitor is varying - no problem, just measure it!

In fact it is simpler to think in terms of charge measurement. Charge can be measured using a stable voltage reference like in integrating ADCs: set a constant current using a voltage reference and a stable resistance and measure the time to charge it to a given voltage, the integral of the current will give the charge. (Of course we still need a stable resistance but here it seems much easier than for stable capacitors).

There are two phases in the measurement. In fact three if I count the cold startup : before the first measurement the software would discharge C2 by connecting Vcomp+ to ground and then setting S1 in the right direction depending on the sign of Vcomp- until zero-crossing on the comparator input is detected.

The first phase is the same as in the previous version: connect the opamp input to S2A and Vcomp+ to Vref+ , then wait until comparator trips counting the number of charge packets.

In the second phase Vcomp+ is connected to ground and the opamp input to Vref- through R2, the software then measures the time to discharge C2 at a constant current Vref-/R2.

Then S1, S2 are immediately set as in the first phase and the process repeats for the next measurement.

I think using two SPDTs with a single comparator should also bring the benefit of compensating for the comparator offset, although I did not attempt to study it more deeply.

If N is the number of packets and T the time to discharge the capacitor then we have :

Q(C2)=N * Q(Cvariable)

Q(C2)=|Vref-| * T / R2

Q(Cvariable)=Cvariable * Vref+

giving

Cvariable=|Vref-| * T / (N * Vref+ * R2)

(NB. If Arduino has differential analog inputs the formula can be made more precise measuring the residual voltage Vcomp- - Vref+, this would improve resolution for the highest capacitance values when N is relatively small)

I'm certainly reinventing the wheel here, there are apparently dozens of patents on capacitance measurement techniques, unfortunately reading patent texts is beyond my skills

I'm eager to know your opinions about this new design.