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STM32F1 LSE Crystal External Caps
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ipek.grgc:
Hello everyone!
I am designing a board with STM32F1 on it. In its oscillator design guide Rev 11 there are recommended 32 kHz crystals and i have decided to use "FC-135" from that recommendation list. It has a load capacitance value of 6pF. CL is 6pF and Cs is taken into account as a value between 7pF to 10pF. According to this formula: CL1 = CL2 = 2(CL - Cs) the resulting capacitance value for external caps appear to be negative since the load capacitance of the 32kHz crystal is small. What does this mean? Am i calculating something wrong? :wtf: :scared:
jhpadjustable:
In the first sentence in section 3.3, Cs is defined as the stray capacitance of the pcb and connections, not series capacitance. If strays are as high as 10pF, your crystal is too far away from the MCU. :)
ipek.grgc:
Thank you for your reply ^-^ I was trying to do the worst case estimation for the stray capacitance value, that's why i take that in to account as 10pF. What would the stray capacitance be in a good designed PCB? Even if i say its 5pF, the calculated external capacitor values would be 2pF. Do i need to put external caps when their values are this small?
jhpadjustable:
That's high. A rule of thumb for 50 ohm impedance-controlled traces on FR-4 is about 3.3pF/in. If my math is correct, a 0.25mm wide trace on FR-4, surrounded by copper 0.5mm away from all edges, with nothing on the other side of the board, has roughly 50fF/mm of parasitic capacitance. So I just put 5.6pF load caps on and hope for the best. :) You can tune the error out, if you really need to (see ST AN2604 for details).
Disclaimer: signal integrity isn't my specialty, not even close.
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