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STMF303 phase shifted PWM
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uer166:

--- Quote from: Siwastaja on June 05, 2020, 05:49:11 am ---Change the duty cycle in the timer ISR so that the change happens during a time window guaranteeing no glitch.
You usually adjust duty cycle in a timer interrupt, synchronously per cycle, anyway, not asynchronously somewhere else.

--- End quote ---

The timers have shadow registers that synchronize the compare value write to the timer period. No glitches should happen even with async writes. I want to have cooperative/hybrid scheduler architecture with no interrupts anyway..
Siwastaja:

--- Quote from: uer166 on June 05, 2020, 05:53:41 am ---
--- Quote from: Siwastaja on June 05, 2020, 05:49:11 am ---Change the duty cycle in the timer ISR so that the change happens during a time window guaranteeing no glitch.
You usually adjust duty cycle in a timer interrupt, synchronously per cycle, anyway, not asynchronously somewhere else.

--- End quote ---

The timers have shadow registers that synchronize the compare value write to the timer period. No glitches should happen even with async writes.

--- End quote ---

Yes, but I think fourtytwo42's point was that these shadow registers won't help with two separate timers, even if they have some synchronization mechanisms. Even if the synchronization makes the timer counters run in sync, the shadow register to working register transfer would happen separately at each timers overflow, possibly causing one of the two timers changing its duty cycle one cycle later, sometimes.

I think this issue is easy to sidestep - if you have a phase offset, you can just write the duty registers in the correct order in a small interrupt-disabled block, even asynchronously - but you can't just ignore it, you need to think about it.
uer166:
I guess I don't understand what the problem is, if I update one PWM after the other, so what? Each individual PWM won't glitch thanks to the shadow register copy, so what's the issue? Each timer has its' own clear inputs an timebases, they basically are independent in every way except a phase relationship that happens to minimize output capacitor ripple.
Siwastaja:
Yes, I agree that in a standard two-phase converter as you explain it, it wouldn't matter if the phases change their duty cycles with unpredictable order and latency.

fourtytwo42 must be thinking some very specific case. I don't see what he has in mind, either, but I understand there might be something to it.
fourtytwo42:
Hi everybody thank you for your clarification, I don't want to hijack the thread but I was concerned about transformer saturation in a large hard switched high frequency bridge converter where the duty cycle is part of the regulation loop and hence updated frequently. Unfortunately the same as sub-harmonic oscillation the inability to change the duty cycle of both halves of the bridge simultaneously could have bad results, I was not convinced sufficiently to risk it and stuck with the PIC solution instead (where a divider flip-flop is part of the pwm). The synchronous with the pwm update is also a feature of the PIC but here it applies to both halves of the waveform simultaneously as the counter source is the same.
I would have preferred to use the STM32 for lots of other reasons. I may be old fashioned but I would never consider using anything like HAL where as the poster mentioned an untold number of instructions are taken to do something poorly documented IMOP.
Once again I apologies for deviating the thread as I realize my concern would probably not affect the OP.
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