Yes, a real world example (piezo or inductive) will have many interesting bits in the signal path.
My mind fills with vapor as I read:
Before applying the ESD protection to my circuit, I've setup a simple spice simulation using a pulse generator that drives a 4KV 4nS pulse into an entry point to see if the ESD protection is ok.
As expected the pulse is properly clamped by the components (I've tried RC filters and TVS).
Well what did you expect it to do? You're the engineer who built the model; you should already know what it was going to tell you.
The real question is (and which SPICE cannot help you with, aside from showing you something that's different from what you measured, if you measured at all), did you construct your simulation model to be sufficiently representative of the real world? And I'm betting not (because to be fair, doing a thorough job of it for just a small range of the full operating space, is HARD).
Examples that come to mind:
- Are your TVS models realistic? If junction diodes, do they incorporate forward recovery effects? (No -- at least, no SPICE model of a diode I've ever seen includes this!)
- If you used latching type TVSs (GDTs, thyristors), do you have adequate models of those too? (Dunno -- possibly not; they're hard devices to model, period!)
- Have you modeled ESL, parasitic C, or even transmission line effects, of your real circuit layout? (Hint: you can't place a TVS just anywhere: if it's hanging off an inch of trace going nowhere else, it's going to do hardly anything!)
- Do you have a realistic model of the power distribution network (relevant to clamp diodes)? Do you have bypass caps nearby or not, and have you correctly modeled the ESL, ESR and so on?
- Did you model the source adequately? An ESD gun is NOT simply a PULSE voltage source, nor is it as simple as the capacitor-and-resistor cartoon given in the standards (there's no possible way a pure RC network would produce the transient waveform also specified, and there's no way a pure RC network would be representative of a real event, or a real test device, anyway!)
- If you have series resistors on input pins, have you modeled their breakdown (if applicable)? Chip resistors are normally rated for around 100V (varies with size), but might arc over closer to 1000V. Likewise, if you have series inductors or ferrite beads, have you modeled their saturation? (Ferrite beads suck if they're carrying any DC or peak AC current at all, and definitely will saturate in the face of a monster ESD wavefront!)
- Just one of many possible nonlinearities that SPICE may forget: BJTs won't draw infinite current, there's a current-crowding phenomenon which causes hFE to fall off at high currents. You can use a zener into a BJT as a clamp (or submit ESD to a BJT structure, say a discrete amplifier input pin), but it won't necessarily behave the way you think it will under such strenuous conditions, even if the simulation says it will be okay.
- Obviously enough, there's no way for SPICE to know when a device has been stressed to failure. If your definition is "parameters (voltage, current, power, etc.) beyond datasheet ratings", then everything is failed immediately, because that is the nature of an ESD or surge event. The failure mode is generally progressive, where microscopic portions of the stressed components have been damaged in some way (if measurable, usually manifest as increased leakage current). Manufacturers' reliability data, inferring from controlled test conditions, is usually the only good way to estimate this sort of damage (which isn't saying much).
The list goes on and on. There are many things that SPICE can and cannot do; it's up to the engineer to figure it out. Often, back-of-the-envelope calculations are much more informative (to-the-point and relevant, without wasting time on excessively complex models, that are poorly defined to begin with!).
Tim
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