Please ignore this post. I am revising the feedback circuit layout.
Here is the revised layout.
(Attachment Link)
I tried to worked on suggestions by @Tooki and @Harry_22 to keep the switching current traces short. I am not sure about layout of output capacitors. Please suggest.
@T3sl4co1l I can remove the ferrite bead if needed.
I'm afraid this is objectively worse than the initial case.
The caution with ferrite beads is more that it might do nothing (saturated by DC current bias), or make overshoot worse (more inductance --> more ringing on/between bypass capacitors). The solution is 1. use an inductor (basically a ferrite bead, with enough air gap not to saturate at rated current), and 2. dampen the network with a lossy bulk capacitor in parallel with the bypass cap, typically using an electrolytic of 10 times the ceramic cap value.
You may find this of interest:
https://electronics.stackexchange.com/questions/713381/correct-placement-of-series-ferrite-beads-to-avoid-dc-disconnect-during-power-cy/713473#713473Here is the revised layout. I have tried to follow the layout guidelines in the datasheet.
Please review and suggest.
: I have intentionally skipped adding stitching via's for now.[/b]
This is better. Connectors on the same end of the board reduces ground loop EMI between them (this will be improved if capacitors are placed near the connectors, preferably with small inductors between existing net(s) and capacitors; improvement may not be necessary to meet commercial levels). C3 doesn't need a polygon on it, it can be routed by trace and vias, and this allows GND to pour fully around U1 to reduce GND impedance. Likewise the SW polygon on L1 isn't doing much, and a little more ground could fill between it and +5V.
This leaves room around all +5V, SW, and the general regulator area, to fill with stitching vias -- "fill" is a rather liberal term, but just one every 5mm or so, plus priority near critical GND pads (U1, C2, C5), will be fine.
Tim