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Struggling with soldering PG-TSDSON-8

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Ah, naming error. 0.65mm pitch is still pretty manageable though. But thermal pads are always a source of concern - yes, too much solder paste on them, and that lifts the package when reflowed -often non symmetrically-, enough to cause soldering issues with the other pads. It's a common problem with QFN-like packages that have thermal pads.

A (stereo)microscope is a must for visual inspection of the soldering of QFN and similar packages IMO. You tilt the board under the microscope. Even if you have a very good eye sight, it's almost impossible to check that without a microscope. Definitely a good investment.

I made some images with my new microscope. On image 2 (top right) you see that the mosfet is not oriented parallel to the PCB.

Not sure if I should try another soldering paste (maybe one with lead?). I used a stencil to put the paste on, so I don't see much to improve there.
I used a hot pan and monitored the temperature of the PCB with an IR camera.

Can try slightly higher peak temp? The flanks didn't quite wet, not that that will take up enough solder but it's inconsistent.  Reflow with added flux should do.

What is that footprint anyway, minimal?  No thermal pads to it?  Via in pad?

The latter can wick up extra solder, which is tricky as the amount wicked isn't reliable; larger vias tend to fill more thoroughly, while fine vias may not much or at all (< 0.3 mm i.d.).  And leaded solder spreads faster than lead-free.

Stencil does have to be used properly; if it doesn't sit perfectly flat, some paste gets stuck/wedged under it, making it look underfilled, then you keep scraping more in, and make a mess.  This is obvious when the stencil is removed; everything's a blobby mess.  Easy enough to fix, just wipe everything clean and try again.

If it's still too much with nominal size pads, then a thinner stencil can be used, or the opening(s) shrunk to compensate.  Large pads typically have webs across them (so the scraper doesn't spring down as much into the opening, keeping amount consistent), not necessary for parts this size I think but you could do exactly the same thing to reduce solder amount here.


I was wondering why the stencil does not always look the same (image 4). But you gave me the answer, it's because of the via. PCB and stencil are from JLCPCB.

It's clear, that the stencil has to lie very flat on the PCB. But I can not change the amount of solder depending on the vias? There must be a process which has some error margin?
I heated the PCB until I measured 200°C on the surface. The melting temperature of the Bi57 solder (SMDLTLFP-ND from Chipquik) is specified @ 138°C.

1) Do you think error margin will increase if I use another solder paste containing lead?
2) Would another footprint such as LFPAK56 be easier to handle compared to PG-TSDSON-8?

I mean I can try again, but because I use a stencil the amount of solder is essentially fixed (as long as the work is done properly). I don't think I can choose the thickness when ordering the stencil from JLCPCB. I also don't know if I could make modifications on the stencil without changing the footprint? Try changing those parameters is my last bet if everything else failed.

There should be no vias in the pads unless they are plugged. An exception are small vias in larger thermal pads under the part, where solder wicking in manageable. But certainly not in the pads for a single terminal. This PCB is problematic by design.


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