Struggling with soldering PG-TSDSON-8

[T_guttata]

Hi

I'm struggling with soldering the PG-TDSON-8 package and wanted to ask for some tipps.

- I have a PCB designed in easyeda and ordered from JLCPCB.
- I use the solder paste SMDLTLFP (Chip Quik Inc. ), which only needs a low temperature
- I use a hot plate and monitor the temperature / time by hand

PG-TDSON-8 is a real pain. Spacings are tiny and you have no chance for visual inspection as there are no legs.Well, you see something, but only a small portion of the solder pads. There is no chance to use a DM for trouble shooting.

Soldering (in my case a mosfet) is just a lottery. I managed to get one right but with several items on the same board, chance for errors is huge.
I don't have a microcope yet, but if I inspect the footprint on the PCB by eye, I doubt that the spacing between the solderpads (0.3mm) is correct. At least the variation is obvious.
Is the PCB quality from jlcpcb not sufficiant for those tiny spacings? SOT23 and 0603 resistors work perfectly.
Should I try a different solderpaste?
Do I need a special coating of the PCB or for the solder pads?
What else can I improve?

Unfortunately the specs I need are mostly only available in tiny packages which are not ideal for prototyping.

Thanks for your help.

[tooki]

Are you sure that’s the right package designator? The PG-TDSON-8 is a pretty big SMD package (about 5x6mm) that’s easily measured with a multimeter, since it has exposed “stubs”, and whose legs are 0.5mm wide on 1.27mm pitch (0.77mm space between legs). Doesn’t sound like what you’re describing.

Please verify that, and provide more info like part number, image of the PCB etc.

[SiliconWizard]

Agree. Apart from the large pad (but should not be an issue if you're using solder paste and a hot plate), this is nothing special. Pin spacing is 1.27mm. How much bigger would you like it to be?
And the pins slightly stick out, so you should be able to touch them with a small probe for testing.

[T3sl4co1l]

Might you be getting incomplete wetting due to the extremely low temperature required?  Or conversely, you can cook that thing to high heaven before melting the plating (pure tin?), by which time whatever flux comes with that paste should be long gone.

The only thing special about DFN/SON is, you need x-ray to properly inspect the center pad.

For hand placement as in one-offs or rework, either:
- Tin the pads beforehand, being careful to apply a minimal amount to the center pad (or use solder wick to remove excess).  Do not tin the component (although in extreme cases, working with old stock components say, I suppose this might be necessary.  Be careful to remove excess solder.)
- Apply flux liberally.
- Preheat the board if necessary: copper planes rapidly spread heat away from the active area, so heat the general area, add blankets to trap more heat around the board, preheat it in an oven or with a proper preheater, etc.  Be patient: expect a heavy board to take some 10 minutes to heat by hot air alone.
- Place the component, freshening up flux if necessary, and apply hot air until the area melts.  The component will slump down and latch in place.  Give it a nudge to seat in place; push it down and around to confirm that it has an adequate volume of solder and that all leads are making contact.  (A toe fillet is sufficient for inspection purposes, but more the merrier.)  If excess solder squidges out when you push it down, try to remove the excess with an iron and wick, or push it aside with tweezers etc.

Or for reflow:
Without all the fiddling around (and perhaps without enough clearance from nearby components to be able to nudge and inspect it as above), you simply need clean surfaces, good paste and a proper heat cycle.  The above has hints at any reason it might fail: oxidized or poorly prepared surfaces, inactive or dry flux, uhh incompatible alloys I suppose (but, the bismuth stuff should be fine still, I mean it contains tin already and most component platings are tin), and too low (doesn't flow) or too high (cooks flux before it has a chance to work; oxidation accelerates) temperature for not enough time.

Note also that bismuth oxidizes faster than lead and tin, and at the much lower temperature you need a special higher-activity flux to keep it moving.  If you have joints going dry for some of the above reasons, you can't really reflow it by applying regular flux and giving it another go.

Tim

[T_guttata]

The package naming is confusing and not clear for me. The MOSFET i try to solder is only 3x3mm: https://www.infineon.com/dgdl/Infineon-BSZ0905PNS-DataSheet-v02_00-EN.pdf?fileId=5546d4626fc1ce0b016ff0a527b0515c

What I forget to mention is that I use a stencil to apply the solder paste.
I‘m currently in holidays, will read the thread again when I‘m back.

[T3sl4co1l]

Not a big deal, 0.65mm pitch is easy to handle, maybe you'll want some magnification if you have poor eyesight, less sure what to do if you have shaky hands.  Same things apply, surface tension is a bit more significant (scales inversely with size).  The nice thing about leadless parts is they tend to self-align, just get it in place, wiggle it a little and surface tension does the rest.

When applying paste with stencil, make sure to have it lay very flat.  Any gap or warp or springback will allow paste to smoosh under the stencil, making it look like you've applied too little, but actually it's too spread out.  Don't be afraid to wipe off and redo it a few times, if you have to.

Tim

[T_guttata]

I don‘t need glasses, but I ordered a microscope anyway because I would also like to make some pictures.
I have a very steady hand, that‘s not my problem.
The top face is not parallel to the board after soldering. I see that the part is moving when the solder is molten, but maybe the big pad is way stronger than the small ones? Is there a reason that the package is highly asymmetrical?

[T3sl4co1l]

Ah, that sounds like too much solder then.

Tim

[georges80]

I hot plate/solder paste a lot of 3x3 (or 3.3x3) FET packages. It is really easy to do and you need a lot less paste than you think. Being a flat package (flat pads under the package) you need only enough paste that when it melts it becomes more like a film of solder rather than a blob.

I use a no clean lead free Loctite solder paste, it works extremely well and has a good quantity of flux mixed into it making prototype assembly very easy.

cheers,
george.

[tooki]

The package naming is confusing and not clear for me. The MOSFET i try to solder is only 3x3mm: https://www.infineon.com/dgdl/Infineon-BSZ0905PNS-DataSheet-v02_00-EN.pdf?fileId=5546d4626fc1ce0b016ff0a527b0515c

While I agree that the naming is often confusing, it’s a lot less confusing if you copy the package name precisely. When you make errors, like writing PG-TDSON-8 instead of PG-TSDSON-8, you make things harder than they need to be! (Both of those exist, so no autocorrecting search can fix it!)

Anyhow, I concur with what everyone says: sounds like too much solder.

[SiliconWizard]

Ah, naming error. 0.65mm pitch is still pretty manageable though. But thermal pads are always a source of concern - yes, too much solder paste on them, and that lifts the package when reflowed -often non symmetrically-, enough to cause soldering issues with the other pads. It's a common problem with QFN-like packages that have thermal pads.

A (stereo)microscope is a must for visual inspection of the soldering of QFN and similar packages IMO. You tilt the board under the microscope. Even if you have a very good eye sight, it's almost impossible to check that without a microscope. Definitely a good investment.

[T_guttata]

I made some images with my new microscope. On image 2 (top right) you see that the mosfet is not oriented parallel to the PCB.

Not sure if I should try another soldering paste (maybe one with lead?). I used a stencil to put the paste on, so I don't see much to improve there.
I used a hot pan and monitored the temperature of the PCB with an IR camera.

[T3sl4co1l]

Can try slightly higher peak temp? The flanks didn't quite wet, not that that will take up enough solder but it's inconsistent.  Reflow with added flux should do.

What is that footprint anyway, minimal?  No thermal pads to it?  Via in pad?

The latter can wick up extra solder, which is tricky as the amount wicked isn't reliable; larger vias tend to fill more thoroughly, while fine vias may not much or at all (< 0.3 mm i.d.).  And leaded solder spreads faster than lead-free.

Stencil does have to be used properly; if it doesn't sit perfectly flat, some paste gets stuck/wedged under it, making it look underfilled, then you keep scraping more in, and make a mess.  This is obvious when the stencil is removed; everything's a blobby mess.  Easy enough to fix, just wipe everything clean and try again.

If it's still too much with nominal size pads, then a thinner stencil can be used, or the opening(s) shrunk to compensate.  Large pads typically have webs across them (so the scraper doesn't spring down as much into the opening, keeping amount consistent), not necessary for parts this size I think but you could do exactly the same thing to reduce solder amount here.

Tim

[T_guttata]

I was wondering why the stencil does not always look the same (image 4). But you gave me the answer, it's because of the via. PCB and stencil are from JLCPCB.

It's clear, that the stencil has to lie very flat on the PCB. But I can not change the amount of solder depending on the vias? There must be a process which has some error margin?
I heated the PCB until I measured 200°C on the surface. The melting temperature of the Bi57 solder (SMDLTLFP-ND from Chipquik) is specified @ 138°C.

1) Do you think error margin will increase if I use another solder paste containing lead?
2) Would another footprint such as LFPAK56 be easier to handle compared to PG-TSDSON-8?

I mean I can try again, but because I use a stencil the amount of solder is essentially fixed (as long as the work is done properly). I don't think I can choose the thickness when ordering the stencil from JLCPCB. I also don't know if I could make modifications on the stencil without changing the footprint? Try changing those parameters is my last bet if everything else failed.

[wraper]

There should be no vias in the pads unless they are plugged. An exception are small vias in larger thermal pads under the part, where solder wicking in manageable. But certainly not in the pads for a single terminal. This PCB is problematic by design.

[T_guttata]

Hm, is this a common design rule not to place any vias in pads? But this would rather result in too little solder than too much?

[T3sl4co1l]

As you can see, you'll get a mix of information from a forum.  You're getting what you paid for...

Via in pad is fine, when done right.  It's unavoidable for thermal pads on QFN, and may be necessary for SON.  It might not be required on DFNs like this, but can be used to improve thermal or electrical performance.

The standouts here are the large size of the vias, and the small size of the one pad in relation.  The, what is that, gate pin?  Don't do that.  The drain, I'd use smaller vias, and 2 or 4 of them.

I already discussed solder wicking above, so I won't reiterate that.

Tim

[wraper]

Hm, is this a common design rule not to place any vias in pads? But this would rather result in too little solder than too much?

There is too little solder on 2 Q8 pads in the middle, sucked away by the via. About pad on the corner, examples where soldering is shown use a PCB different layout to bare pads shown.

[EPAIII]

I am not sure a hot plate is the best way to re-flow solder. Heat from below has to penetrate the PCB substrate which, in addition to being an electrical insulator, is probably a fairly good insulator against heat. And the top, where the IC sits is exposed, at least somewhat, to the air so it is cooler than the copper traces. I can see where it is difficult to get enough heat into that large pad.

I have an old toaster oven that has one element burned out. By testing with an oven thermometer inside it, I found a heating period that approximated the recommended heating curve for re-flow soldering. And points in time to turn off the heating element and to open the door about an inch to increase the cooling effect. It provides a more uniform heat - top and bottom. I believe this, more uniform application of heat, is how the recommended re-flow temperature curves were developed.

It seems to work well with the parts I have tried it on. I have not tried it on any parts like your PG-TDSON-8 with such large pads.

[T_guttata]

As you can see, you'll get a mix of information from a forum.  You're getting what you paid for...
Tim

While I know that phrase I don't understand it in this context?

What via diameter would you use? I just did my first PCB some months ago and regarding via diameter I just trusted easyeda. Standard diameter is 0.6mm there.

About pad on the corner, examples where soldering is shown use a PCB different layout to bare pads shown.

Don't know what you intend to say? I have used the footprint various times and the vias are not always placed the same.

I am not sure a hot plate is the best way to re-flow solder. Heat from below has to penetrate the PCB substrate which, in addition to being an electrical insulator, is probably a fairly good insulator against heat. And the top, where the IC sits is exposed, at least somewhat, to the air so it is cooler than the copper traces. I can see where it is difficult to get enough heat into that large pad.

I have an old toaster oven that has one element burned out. By testing with an oven thermometer inside it, I found a heating period that approximated the recommended heating curve for re-flow soldering. And points in time to turn off the heating element and to open the door about an inch to increase the cooling effect. It provides a more uniform heat - top and bottom. I believe this, more uniform application of heat, is how the recommended re-flow temperature curves were developed.

It seems to work well with the parts I have tried it on. I have not tried it on any parts like your PG-TDSON-8 with such large pads.

Well, yes, my method is not ideal. I'm prototyping, I'm no electronics manufacturer. I googled a lot and as far as I understand, there is no proper solution out there which is affordable, lets say <$500. Because all proposed solutions have severe drawbacks, I just tried the one which I can do for free: using my inox pan and an inductiion cooker.
SOT23 and small resistors worked perfectly fine, I just have some trouble with this PG-TSDSON-8 package.

What I have learned so far is that vias can cause errors and therefore I will try to place all vias outside of pads in the future. Maybe I have to change my PCB and reorder it.

But I repeat my two questions from the previous post:

1) Do you think error margin will increase if I use another solder paste containing lead?
2) Would another footprint such as LFPAK56 be easier to handle compared to PG-TSDSON-8?

Once I read that breadboards are bad because you are actually trouble shooting the breadboard more often than the actual circuit.
Now, I'm doing a PCB but I'm trouble shooting the PCB and not my actual circuit^^

I would have bought the PCB fully assembled, but jlcpcb does not have the mosfets I need. Is there any other supplier for prototyping?

[wraper]

About pad on the corner, examples where soldering is shown use a PCB different layout to bare pads shown.

Don't know what you intend to say? I have used the footprint various times and the vias are not always placed the same.

That soldering issues on examples do not represent via locations as shown on the footprint, so your argument

Hm, is this a common design rule not to place any vias in pads? But this would rather result in too little solder than too much?

is not quite relevant towards my previous comment. As I have not seen an example of soldering with particular via placement.
When you get solder sucked into via, part gets pulled towards pcb in that patricular location. Which may cause solder squeezing out in other locations without vias where solder has no other places to go to.

[tooki]

1) I don’t think the alloy is the problem here. If the component is riding up on the solder, it either a) hasn’t melted fully (up which is unlikely with your low-temp solder), or b) there’s too much solder (which is VERY easy to do, especially with small parts).

If I had to place a bet, I suspect that applying a lot less solder to the large pad would solve the problem. The vias in the pads simply make it harder to determine the right amount, since some pads will suck up more solder than others. With that said, err more on the side of less solder than of more. The issue here is that some pads have too little solder, others have too much. The vias are one issue, as said, but paste application is likely another issue.

What t3sl4co1l said about the stencil needing to be perfectly flat against the board cannot be understated: if it rises even just a fraction of a millimeter, you WILL apply much more solder than intended. It takes practice to get a good technique that doesn’t smoosh paste under the stencil. The angle, pressure, and speed of the squeegee (as well as its material; IMHO metal is better) make a difference.

If a paste print isn’t perfectly clean, clean the PCB and the stencil and try again. If there’s any paste residue on the bottom of the stencil it will cause a gap allowing excess paste to be applied.

2) The D2PAK package (and its many close relatives, like DPAK and LFPAK56) are far easier for a beginner to work with, since they’re bigger, and can easily be hand-soldered.

[tooki]

About pad on the corner, examples where soldering is shown use a PCB different layout to bare pads shown.

Don't know what you intend to say? I have used the footprint various times and the vias are not always placed the same.

That soldering issues on examples do not represent via locations as shown on the footprint, so your argument

Hm, is this a common design rule not to place any vias in pads? But this would rather result in too little solder than too much?

is not quite relevant towards my previous comment. As I have not seen an example of soldering with particular via placement.

I think your (generally quite understandable) English is having a bad day today; I can’t figure out what you mean, either!

When you get solder sucked into via, part gets pulled towards pcb in that patricular location. Which may cause solder squeezing out in other locations without vias where solder has no other places to go to.

To be very clear, it’s not that the via is sucking the chip down, it’s that the excess solder on the other pins is lifting the chip up. I say this because the same effect happens whenever you have excess solder on a pad, even if none of the pads have vias.

[wraper]

When you get solder sucked into via, part gets pulled towards pcb in that patricular location. Which may cause solder squeezing out in other locations without vias where solder has no other places to go to.

To be very clear, it’s not that the via is sucking the chip down, it’s that the excess solder on the other pins is lifting the chip up. I say this because the same effect happens whenever you have excess solder on a pad, even if none of the pads have vias.

Yes it is sucking the chip down with almost zero distance to PCB left due to surface tension/capillary action. If there was no solder paste at all on the pad with via to begin with, chip would sit straight, holding on other pads. It's not an excess solder, it's almost no solder on the pad with via what causes the issue. Once the part does not sit straight due to lack of solder on some pad, then you likely will also have solder squeezing out from some other place.
https://www.eurocircuits.com/pcb-assembly-guidelines-solder-escape-wick/

[T_guttata]

To reduce the amount of speculation, I just soldered again one mosfet and made some pictures with my lovely new microscope :-)

In this case, there is only one via inside a pad, but judged just by optical inspection I would say that this parcitular pad is not the problem?

How do you judge the amount of solder? The stencil is 0.18mm in thickness and I pressed it flat while applying the solder.

I heated the pan until I measured 200°C at the PCB surface and then let it cool down. It took about 1.5 mins to get to 200°C.

[tooki]

When you get solder sucked into via, part gets pulled towards pcb in that patricular location. Which may cause solder squeezing out in other locations without vias where solder has no other places to go to.

To be very clear, it’s not that the via is sucking the chip down, it’s that the excess solder on the other pins is lifting the chip up. I say this because the same effect happens whenever you have excess solder on a pad, even if none of the pads have vias.

Yes it is sucking the chip down with almost zero distance to PCB left due to surface tension/capillary action. If there was no solder paste at all on the pad with via to begin with, chip would sit straight, holding on other pads. It's not an excess solder, it's almost no solder on the pad with via what causes the issue. Once the part does not sit straight due to lack of solder on some pad, then you likely will also have solder squeezing out from some other place.
https://www.eurocircuits.com/pcb-assembly-guidelines-solder-escape-wick/

The same effect happens with no vias around.

Let me repeat this: you get the same thing with NO vias. It IS the excess solder that causes lopsidedness. (Even if all pads have even solder distribution, if the solder amount is excessive, then you get chips floating around and cooling crooked.)

It’s not the via pulling down, it’s the excess solder pushing up. “Almost zero distance to the PCB” is precisely how a good joint is supposed to be. Surface tension and capillary action  apply to all solder joints, it’s nothing unique to a via.

[T_guttata]

I posted a picture where you precicely see, how much solder there is. Is this really too much???

[uer166]

I would start by ditching the low melting temp solder, I've had serious issues with it like lack of wetting (just like in your case), and serious outgassing of the flux post-soldering ruining conformal coats. I would recommend Kester EP256, easy to use and wets really well. Based on your pictures, there is too much paste (try thinner stencil), but nothing too bad, so just try switching paste.

[T_guttata]

Ok, this Kester EP256 is not available on digikey. But I will try another paste with Sn63Pb37.

[uer166]

Ok, this Kester EP256 is not available on digikey. But I will try another paste with Sn63Pb37.

It's available on Amazon. I can't comment on normal Sn63Pm37 paste, but EP256 was specifically designed to be easy, and it shows.

[T3sl4co1l]

That particular attempt looks fine, yes.  The solder balls aren't great, and it's not clear how much wicked into that via (evidently not much). That might just be process variation.  Doing another dozen or so would give, at least a starting point, as far as statistical samples go.

Tim

[tooki]

I posted a picture where you precicely see, how much solder there is. Is this really too much???

I think so. But it’s easy to test: stencil it on, then use a curved scalpel blade to carefully remove some paste before placing the component. For example, try removing 1/3. Then see how it reflows.

Since you have a microscope, you don’t need to rely on a full fillet on each pin to ensure it’s connected: use the microscope to look at the joint from a diagonal. You should be able to see whether it’s flowed to the pad and pin.

[T_guttata]

I tried again with a different solder paste, but unfortunately it does not really look better?

I don't have a scalpel blade to try to remove some solder. The stencil was way more expensive than the actual PCB and therefore I would assume, that it actually works.

What's usually the thickness of the stencil? Maybe jlcpcb does not a good job in this regard?

Anyway, I will certainly switch to a LFPAK56 footprint. I want to be able to solder it correctly with 99% chance, otherwise I only end up debugging.

Maybe I could also order a fully assembled PCB from https://www.eurocircuits.com/? I just did not find any price indication for assembly.

[tooki]

I tried again with a different solder paste, but unfortunately it does not really look better?

I don't have a scalpel blade to try to remove some solder. The stencil was way more expensive than the actual PCB and therefore I would assume, that it actually works.

What's usually the thickness of the stencil? Maybe jlcpcb does not a good job in this regard?

Stencils are intended for precision application in multi-thousand-dollar paste printing machines. They were never intended for manual use. Chances are you think you’re using it properly, but aren’t. (Using stencils manually is HARD. I was just talking about that the other day with a guy at work — a literal graybeard who started working in electronics before I was born — because of some difficulty he was having with getting clean paste prints for some components. And that’s with expensive European-made boards and stencils. It’s very hard to support a stencil properly when using them manually. They need high rigidity by being mounted into frames under high tension, not flopping around.)

Tiny parts with tiny pads simply leave no room for error. The tiniest slip and you get paste under the stencil, which raises it up and increases the amount of paste applied.

Honestly, the last picture there doesn’t look bad at all. But yes, if a larger package is available and PCB space allows, use it, as it will make your process more predictable and easier to inspect.

FYI, with JLCPBC stencils, the vast majority of the cost is shipping, due to the dimensions of a whole stencil. But you can apparently ask them to cut the stencil down to size for manual use, allowing it to be shipped in the box with your PCBs.

[T_guttata]

I was looking for very low Rds_on mosfets smaller than the TO220 package and ended up with this PG-TSDSON. The TO220 package would be too big, but the LFPAK56 is 5x6mm and totally fine. I will try it.

Stencils are intended for precision application in multi-thousand-dollar paste printing machines. They were never intended for manual use.

I doubt the package size of 3x3mm was designed for hand fabrication^^

FYI, with JLCPBC stencils, the vast majority of the cost is shipping, due to the dimensions of a whole stencil. But you can apparently ask them to cut the stencil down to size for manual use, allowing it to be shipped in the box with your PCBs.

Yes, I already reduced the stencil size until it does not increase shipping chost. $2 for 5 PCBs, $7 for the stencil and approx $20 for shipping^^