Suggestions wanted for N-ch MOSFET with really low VGS(th)

[HwAoRrDk]

Can anyone suggest an N-channel MOSFET in SOT-23 package that has a really low V_GS(th)? I need something that turns on fully (or almost fully) with as little as 800mV V_GS.

You're probably wondering why I need such a thing.

I'm using the MOSFET to gate a reset signal (active-low) with a couple of power-good signals, so that the output reset signal does not go high unless both PG signals are also high. See attached schematic. I thought I should be able to use an N-channel MOSFET here because while the RST signal is 3.3V, I have 5V available to pull the gate up to, which gives me a nice 1.7V V_GS. A common transistor like a BSS138 (max. V_GS(th) of 1.5V) would do that nicely.

But... I failed to take into account voltage rail tolerances. In a potential worst case scenario, where 3.3V is 10% high (3.6V) and 5V is 10% low (4.5V), I've only got 870mV to play with. A BSS138 won't properly turn on like that, so will drop a lot of voltage drain-to-source, making it lucky if the reset signal makes it out the other side above a logic-high threshold (2V).

So far I've found the Si2302, but only the actual Vishay part has a V_GS(th) max. of 0.85V, whereas none of the widely available clones I've seen match that spec - all are somewhere between 1.0 to 1.5V. But I'd rather not be stuck with one part from one manufacturer.

[Slh]

How about an npn? A 2n3904 or similar will probably do the job.

[Kim Christensen]

Why don't you use a logic chip instead? (Replaces D1, R14, & Q3)

[Peabody]

What is the nature of the PG_3.3V signal?  Is it 3.3V when high, or is it open drain?

I'm wondering if pin 3 of D1 could be the reset signal you want, so you don't need the mosfet at all.  It seems pin 3 would be low if either input is low.  The complication is that if PG_3.3V is 3.3V when high, then your reset signal would be about 3.6V.  But if both PG_3.3V and the /Reset output of the monitor chip are open drain, then your reset would be 5V when both inputs are good, and 0.3V if either input is not good.  Or you could pull pin 3 up to 3.3V instead of 5V.  Then your reset would be 3.3V when good, and 0.3V if either input is bad.

[Peabody]

But you said "gate" the reset, so maybe this would work.

[Peabody]

No, I think I was right the first time.


Edit:  The datasheet for the MAX803 says its Reset output is open drain.  If PG_3V3 is also open drain, then you don't even need D1.  But even if it's push/pull, you only need a 1N4148 on that line.  You don't need a diode for the MAX803 line.

[mariush]

Digikey has some Toshiba mosfets with Vgs as low as 0.35v but Rds(on) was just average ( typical 2.4 ohm, max 9 ohm with vgs = 1.2v)

SSM3K35CTC https://www.digikey.com/en/products/detail/toshiba-semiconductor-and-storage/SSM3K35CTC-L3F/5403447

SSM3K35AMFV https://www.digikey.com/en/products/detail/toshiba-semiconductor-and-storage/SSM3K35AMFV-L3F/7394058

Rohm RU1J002YNTCL  is min 0.3v max 0.8v Vgs threshold with around 3 ohm (max 9 ohm) Rds(on) at vgs=0.9v  : https://www.digikey.com/en/products/detail/rohm-semiconductor/RU1J002YNTCL/5042819

Not sot-23 but easy to solder.

[Someone]

Rohm RU1J002YNTCL  is min 0.3v max 0.8v Vgs threshold

Low voltage drive(0.9V) makes this device ideal for partable equipment.

Party

[HwAoRrDk]

Why don't you use a logic chip instead? (Replaces D1, R14, & Q3)

After considering my options, I think I may actually change to a triple-input AND gate instead. A 74LVC1G11 should do the trick.

The reason why I was going with diodes and a MOSFET was because I wanted to try re-using components I already had on the board anyway, without introducing an extra part. If using a different MOSFET here, I would change other instances to the same part.

But I don't really like the idea of using a part that only comes from one manufacturer, which it looks like I'd have to do to get a MOSFET that meets the requirements. I was hoping there might be have been some jellybean-ish part out there that I wasn't aware of. Thanks anyway, all.

[HwAoRrDk]

But you said "gate" the reset, so maybe this would work.

No, I think I was right the first time.

I'm not sure what you were trying to do with those circuits, but both miss the point, which is to not allow a high on the RST input to propagate to RST_OUT unless both the output from the MAX803 and PG_3V3 are also high. Those circuits just pass RST straight through to RST_OUT.

[Peabody]

I'm not sure what you were trying to do with those circuits, but both miss the point, which is to not allow a high on the RST input to propagate to RST_OUT unless both the output from the MAX803 and PG_3V3 are also high. Those circuits just pass RST straight through to RST_OUT.

I guess I was assuming that RST is not a low-impedance source, and that RST_OUT doesn't need to be low-impedance either.  What's the origin of the RST signal, and how much current does RST_OUT have to source when it's high?  If it's not a lot, then my circuits would work if you add a series resistor to RST.  Something like the circuit below.  But if RST_OUT needs to supply significant current to turn the downstream devices on, then your mosfet would be necessary, or maybe an NPN.

[ArdWar]

output reset signal does not get asserted unless both PG signals are also asserted.

Hmm, but all of your proposed schematics allow reset to be asserted if any of the PGs are asserted (instead of both). If you only allow a reset if both PG are asserted (and assuming all reset are active low) then you just need to OR (positive logic) the three signal. If you want to only allow a reset if any PG are asserted then you need to OR the reset with (PG1 AND PG2).

I agree that it would be much easier and more reliable to use glue logic.

[HwAoRrDk]

Hmm, but all of your proposed schematics allow reset to be asserted if any of the PGs are asserted (instead of both). I agree that it would be much easier to use glue logic especially if you need an AND there.

Ugh, I mis-typed the wrong word there. I meant to say "high" instead of "asserted" - "so that the output reset signal does not get asserted go high unless both PG signals are also asserted high".

[ArdWar]

Well, then that makes the whole thing a lot more sensible. Just a normal multiple power health check instead of what I thought some weird redundant architecture.

If all three inputs came from open drain outputs and the signals are actually PG/NRST then you could simply tie them all together, with pullup to output level (3v3?). Put a backward diode (just like above) for any of the signal that aren't open drain. No need to put diodes on open drain signals (unless you pull each of them up individually, which is unnecessary).

[Peabody]

But if you use glue, like the three-input AND gate, then each input that is open drain has to be pulled up.

I'm still unclear about the nature of the RST and PG_3V3 inputs, as well as what RST_OUT needs to do.  I'd really like to see the rest of the circuit.

A further complication is the question of what should happen when an input is absent (when the device generating the input isn't powered up).  Presumably it should be the same as when it is low, but if it is absent, it won't be low.

Well, I too was thinking along the lines of making it simpler, and offered some circuit suggestions, but was probably premature in doing that.

[HwAoRrDk]

The RST input signal is push-pull, not open-drain. Only PG_3V3 and the output from the MAX803 are open-drain. The RST (and 5V) will always be present (i.e. not floating) before the 12V and 3.3V are even powered up - hence why I want to gate it on condition of those power rails being good. The thing producing the RST signal is not aware of the power-up sequencing/timing, so there is a concern it will de-assert RST too soon. The RST is actually for control of an off-board device, which is where RST_OUT goes.

[tggzzz]

https://www.digikey.co.uk/en/products/detail/analog-power-inc/AM2336N-CT/22540112
is in stock.

Took me 2 minutes to find that using Digikey's parametric search
https://www.digikey.co.uk/en/products/filter/transistors/fets-mosfets/single-fets-mosfets/278?s=N4IgjCBcpgbFoDGUBmBDANgZwKYBoQB7KAbRABYAGAVgGYBOekAXQIAcAXKEAZQ4CcAlgDsA5iAC%2BBWJXjQQySOmz4ipELQDsADkZNWITtz5CxkggFoATAgVQBAV1XFIZaiwmegA

[Terry Bites]

The diode NAND has poor noise imunity.
A quad NAND might be a better choice here or a couple of dual NANDs eg 74LVC2G132
A couple of smart arse 74LVC1G98GVs will do it too
Probably cheaper than the other bits and a lot more reliable.
A smaller footprint too.

[Peabody]

The RST input signal is push-pull, not open-drain. Only PG_3V3 and the output from the MAX803 are open-drain. The RST (and 5V) will always be present (i.e. not floating) before the 12V and 3.3V are even powered up - hence why I want to gate it on condition of those power rails being good. The thing producing the RST signal is not aware of the power-up sequencing/timing, so there is a concern it will de-assert RST too soon. The RST is actually for control of an off-board device, which is where RST_OUT goes.

So what is the nature of the off-board device's input pin that receives the RST_OUT signal?  How much current will it sink?  Does it have a pullup resistor?