Different between two type of inverter gate ?

[Nhan95]

Could you tell me the difference between 2 inverter circuit, which is better and why ?

[SeanB]

Lower one has active pull down and pull up when changing state, and is also capable of driving a larger capacitive load and also can operate at a higher frequency into a specific trace length than the first.  Drawbacks are that there is a region in the middle of the logic level ranges where both transistors are turning on and this causes a big supply current spike, so there is a limit on the on resistance of the active devices, plus there is a power dissipation peak there on slow changing inputs.

First one at least has a fast falling edge, but the rising edge is slow, from the RC time constant of the output loading and traces. However it does not have a current spike, and with slow edges acts as a somewhat linear amplifier. Current draw when output is low however means a constant power dissipation, and a different current between high and low outputs.

The first is not good to clock logic circuits that use latches, as it will have too low a rise time, but will do fine for simple gate logic, while the second is capable of driving with a much reduced rise and fall time.

[German_EE]

The first schematic has an output which is pulled down hard but the pullup is a simple resistor.

The second schematic has an output which is pulled up OR pulled down hard, this sort of output can source or sink much more current

[TheoB]

The first one was used before complementary mos processes existed. They simply only had NMOS and resistors, no PMOS.  It also allowed to tie multiple inverter outputs together to create a wire-orred NOR gate. But the static current when the output is zero really is a waste of energy. You can find this on wikipedia as well  https://en.wikipedia.org/wiki/Inverter_(logic_gate)