Switching losses@ MOSFETs, Caps and Diodes

[KoF]

Hi guys,

right now, i try to design an full Bridge Class D Amp with ~100W/24V @8Ohm  (I know, one of hundred thousand projects - sorry... ).
I finished all my calculations and started to simulate the power stage in LTspice and it works well as expected (in LTspice)!

But then, i did some "simulated" measurements and get shocked!
The switching frequency is about 250kHz (I would prefer up to 400kHz for the "physical" Amp)
My MOSFETS (IRFH5215) has needle peak (turn on) losses of up to 350W and (turn off) of up to 40W for ~10ns and less.
I even tried to reduce the peak current by an inductor in front of the Mosfets with turn on and off snubber without great success 
Are those needle peaks of power losses acceptable for ~10ns @250kHz?

the Mosfets are driven by LTC4444 drivers (in the simulation) with an 10R resistor (turn on) at the Gate and in parallel (for turn off) a Diode with 2.2R in Series. Between Gate and Soure I placed an 4k7 resistor.

The Mosfet body diodes (both Mosfets hi and low) are bypassed with 30BQ060 schottky diodes. They get current peaks with up to 6A for about 800ns. The Datasheet of the 30BQ060 says I[f] average of up to 3A and I[fsm] up to 1200A @ 5µ sinus.  Is my selection suitable? (I guess (or better hope so) yes, or am I wrong?)

I think the losses are okay, because those peaks are so damn short - but I'm not sure...

One last question (I know, i asked to much ) is about the output LC filter.
I would like to use X7R or X5R caps instead of polycarbonate foil  caps (cheaper, smaller, easy to get, surface mount,more types,...). To reduce the peak current, I would use more smaller values in parallel instead of one huge on. I know, for an Class A or AB ceramic caps are not suitable, but for Class D? Is this decision okay (especially in consideration of the switching frequency) - any advices?

Sorry for my worse English slang and for my (maybe) stupid questions. I never designed such power stages before. Usually I design FPGA Layouts...

Thanks for your help
Greetings from Germany

[Kremmen]

In an application like this there are 2 separate loss mechanisms in the switch: conduction losses and switching losses

Conduction losses can be approximated by P = Rdson * Id i.e. the familiar Ohm's law.
More difficult is to calculate the switching losses. If the application is a pure hard-switching one where the full voltage is switched to a dead load (i.e. there is no resonance effect that could be used to help) then what happens is that when you apply the gate voltage, first the drain current rises and only after it has reached more or less the final level, only then will any appreciable reduction in drain-source voltage be apparent. So there is a brief moment when the device dissipates the entire V * I product. The peak power will be significant but the average power may not be that much. Of course the average is directly impacted by the frequency of switching.
When switched, the gate voltage evolution progresses along a curve with a couple of knee points. These knees are caused by internal capacitances that comne into effect at various electrical field intensities between the internal elements. Without going deeper into that, different types have different characteristic capacitances and gate charges. The knee points in Vds and Id are related to the gate voltage knee points so the actual losses are naturally different for different devices.

One way to calculate the average switching power dissipation is to calculate or estimate the energy dissipated during one switching event (on, off) and then multiply this by the switching frequency to get the average power.

[KoF]

Hi Kremmen,

I double checked the losses before I started the simulation. I should be around 0.6W @250kHz (sum of duty times Pon plus Pswitch_on and Pswitch_off) in worse condition per FET.

But I was wondering about these extremely high needle peaks! I guess they were unhealthy for the FETs 

[HackedFridgeMagnet]

Hi Kof
In LTSpice you can graph the instantaneous power like the voltage and current by holding down the alt key (I think) when selecting.

I think you could get this high instantaneous power by not having enough dead time between the high and low side gate drivers. So for just a fraction a second you have what is close to a dead short across your output rails.
Just somehow delay the gate turn on by a further 10ns.

[KoF]

Attached is my "simple" Powerstage.




@HackedFridgeMagnet
I know, this was one of my measurement...

[Kremmen]

Hi Kremmen,

I double checked the losses before I started the simulation. I should be around 0.6W @250kHz (sum of duty times Pon plus Pswitch_on and Pswitch_off) in worse condition per FET.

But I was wondering about these extremely high needle peaks! I guess they were unhealthy for the FETs 

Well that is what happens during hard switching. Of course there are limits but it is heat that destroys the component and unless the heating is such that it explodes right away, it should not be a big deal. The average power is low and dissipates normally. If memory serves i have calculated peak powers of several kilowatts in some applications without any adverse effects to the switches. Of course those switches were a bit more robust than yours but still.

Edit: Shoot through that HackedFridgeMagnet refers to is unlikely with a dedicated half bridge controller. Oops wait, did the 4444 have separate control inputs for the high and low switches? In that case it is of course possible but somehow i don't think that is the case. The peak power is quite plausible for normal hard switching event.

Also i didn't see anything immediately suspicious in the circuit. One thing i noted was that the gate discharge on the right side lacks the 2.2 ohm resistors so turn-off will be snappy. One should pay attention to the gate drive intensity to find the sweet spot between minimizing switching losses and avoiding excessive ringing. Driving the gates too hard will cause MHz range oscillations that can go up to 100s of MHz. That kind of EMI will spread and cause all manner of nastiness.

[KoF]

Okay, so it seams to be "normal"

Did you take a look at the schematic? Do you have ideas for improvements?

What is about my question with the caps and diodes? -> sorry

[Kremmen]

Let me take another look on that. I will comment unless someone else beats me to it.

[HackedFridgeMagnet]

I think all your diodes need to be shottky, according to the datasheet something like 5819 for 1 amp or mbrs340? for 3 amps.
1n914 is a small signal diode, don't use for this job.
I think the instantaneous power problem is only because of the limitations of the LTSpice model.
The data sheet says that the half bridge is shoot through protected. This should be fine.
Not sure if you need all the stuff around the gate, although the 10 ohms is good.
Beat ya Kremmen.


But you can still comment.

[KoF]

So I use the 914 diode just for the capacitive voltage pump of the driver and for discharging the gates... I use a 30BQ060 (60V 3A Schottky like the mbrs340 but with 60V) at the power part.

[KoF]

Oh damn... I made an mistake!
The Fet M2 has an wrong gate wiring... it should be like M4!

[Kremmen]

OK, nothing dramatic. The M3,M4 gates are different from M1,M3 gates and i can't see why that should be the case.
If the driver is protected against shoot through then that makes one of my comments moot; the comparators don't ensure any particular order of signal transition. I know this is the topology often shown in books and papers, but it has a weakness: the comparators must be well matched to switch around exactly at the same time every time. If they have different input bias that may not happen and the result could be less that desirable. Since one signal is always supposed to be the inverse of the other, a circuit that ensure this at all times could be more secure. But maybe it does not matter here.
The output filter is a relatively critical component of a D class amplifier. Component selection is important and with capacitors you must bear in mind that they are not ideal components. The self inductance of certain types of caps make them useless on higher frequencies. After a certain cap specific corner frequency the response turns progressively more inductive until whatever is labeled on the component has lost all meaning. What i would do is put a high quality film cap in parallel with a ceramic (NPO!) cap that extends the corner frequency well beyond your switching freq.
Another thing you might consider is to divide the inductances and capacitances in the output filters to turn the 2nd order filter into a 4th order one. That would improve the response under varying load impedance and also you could raise the corner frequency perhaps. That might not be so important of itself but the signal phase would track more linearly.

[KoF]

Thanks for your advice! 

I guess the selected comparator (a dual one, means hopefully only one DIE with nearly identical features) will do his job fine.
I tried to expand the dead time by using the 10R Resistor to switch it on smoothly an discharge a few times faster by the diode (the resistor in series on one side was just to decrease the current a bit for testing)
By the way, once (totally different project, years ago) I worked with such an 4x comparator LM339 jellybean... the problem was, that one brand I used was not able to switch more than 3 channels at once - I tried a few other from same brand with same results...  I changed to one of Fairchild and it works well on all channels at the same time as expected...

The Filter.. yes... I read a bit about... I will change the Caps to foil caps from WIMA. Once I had a bad experience with an awful fizzling noise in the past by capacitive charge reversal and heating up till glowing (a guy asked me: Hey there is an red LED and an piezo on the board... -> and then it started to smell  but it was not my fault! The circuit witch produce the swing was damaged before - nice effect

One last question:
For the first prototype I would keep it simple without feedback (open loop design). Is this recommendable? 

[Kremmen]

You are familiar with feedback systems in general? A basic principle of feedback amplifiers is that the forward gain is very high and the closed loop gain is determined purely by the gain of the feedback path. Now if your front end and VAS are designed to be feedback amps as i am sure they are, you cannot leave the feedback out. The open loop gain will be high enough to drive the power stage directly from rail to rail with no useful output signal.

P.S. If you can show the schematic for the front end that would make commenting easier.

[T4P]

Just be careful about through hole caps.
I can't access my element14 page right now because something went wrong so i can't judge.

Use SMD poly caps and a NPO(C0G) cap in parallel