| Electronics > Projects, Designs, and Technical Stuff |
| TDM Audio transport. Have I f!cked up this design? |
| (1/1) |
| Yansi:
Hello, I have designed an application, that uses the CS4244 audio codec. Datasheet here. I wanted to be able to operate at both 48k and 96k sample rate. I have fixed the MCLK to 24.576MHz. Now I am not sure if I have fucked up. :o :-\ For 48kHz operation, I designed it so I'll have 12.288 MHz SCLK at 256fs and for 96kHz operation SCLK will be same as MCLK, 24.576 MHz at the same 256fs. My TDM signal source does not support frame any larger than 256bits (256fs). Now reading through the datasheet, I'm not sure whether this is possible after all. Relevant chapter in the datasheet is for example "6.3 Clock & SP Select (Address 06h)". And then there is this very worrying note below the table "SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE" at page 19, saying: "26. MCLK must be synchronous to and scale with FS". Another relevant is "4.4.3Slave Mode Clock Ratios". I have fixed 24.576MHz, so it does not scale. :palm: Y. |
| Yansi:
I try to answer myself, as how do I (or at least did understand the damn datasheet) when I have designed the board in March: 48kHz shall be SSM (Single Speed Mode). 96kHz shall be DSM (Double Speed Mode). That is clear. According to Table 5. page 27, I in fact can have MCLK at 512fs and SCLK at 256fs, in a SSM, 48kHz. At 96kHz, there is no other option than 256fs MCLK and 256fs SCLK. Good. If I understand the above correctly, I set the device as following, regarding the "6.3Clock & SP Select (Address 06h)" register: BaseRate = 48k (both for 48kHz and 96kHz of my operation modes) MasterClockRate = 010 (512xFs in Single Speed Mode or 256xFs in Double Speed Mode) and the only difference shall be the SpeedMode = SSM for 48k and DSM for 96k. Done. Hopefully, I am correct and these two posts will remain a useless complaint. Thanks for any moral and tech support on this one ;D I'd rather not bodge the PCB in any way. Y. //EDIT: Typos. |
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