I try to answer myself, as how do I (or at least did understand the damn datasheet) when I have designed the board in March:
48kHz shall be SSM (Single Speed Mode).
96kHz shall be DSM (Double Speed Mode). That is clear.
According to Table 5. page 27, I in fact can have MCLK at 512fs and SCLK at 256fs, in a SSM, 48kHz.
At 96kHz, there is no other option than 256fs MCLK and 256fs SCLK. Good.

If I understand the above correctly, I set the device as following, regarding the "6.3Clock & SP Select (Address 06h)" register:
BaseRate = 48k (both for 48kHz and 96kHz of my operation modes)
MasterClockRate = 010 (512xFs in Single Speed Mode or 256xFs in Double Speed Mode)
and the only difference shall be the
SpeedMode = SSM for 48k and DSM for 96k. Done.
Hopefully, I am correct and these two posts will remain a useless complaint.
Thanks for any moral and tech support on this one

I'd rather not bodge the PCB in any way.
Y.
//EDIT: Typos.