Author Topic: MAX1873 Charging IC - Please Help  (Read 2488 times)

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Offline lucent567Topic starter

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MAX1873 Charging IC - Please Help
« on: August 07, 2016, 12:48:02 pm »
Hello,

I've designed a circuit based on the MAX1873: https://datasheets.maximintegrated.com/en/ds/MAX1873.pdf
(I've also attached the application design from the datasheet and the application design of the evaluation board)
I need to charge 4 cell Li-Polymer batteries (connected in series).
The max voltage of each cell is 4.2V so I set the charging target voltage to be 16.4V which is 4.1V per cell (just below the maximum).

Also, I don't need the input current monitoring feature so I shorted the pins CSSP and CSSN to DCIN as written in the datasheet:
"Short CSSP and CSSN to DCIN if the input-source current-limit feature is not used".

I chose CBATT to be 33uF as indicated on page 8.
ICH/EN is connected to VREF via a 10K ohm resistor.
I used a resistor of 0.07ohm for RCSB to get a charging current of around 2.8A.

However, now that everything is soldered and all I get a constant charging current of 70mA. This might be OK if the battery pack voltage is close to 16.4V but that is not the case. The voltage is at around 15V so this does not make sense.

I was wondering if anybody had any clues as to what could be wrong in my design?
Please take a look at my design attached.

Thanks,
David
« Last Edit: August 07, 2016, 12:53:10 pm by lucent567 »
 

Offline Ton

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Re: MAX1873 Charging IC - Please Help
« Reply #1 on: August 09, 2016, 06:49:15 pm »
I will give it a go  :)

and welcome to the forum.

I cant find a input capacitor, the sample board have a 47uF (low esr) at the source of Q2, without a local input capp, the current pulses have to come all the way from your power supply. creating switching noise and voltage drop all the way.

If you can show us the layout or some detailed pictures of the circuit we might be able to give more advice.

In my experience then this kind of missing output current quite often is due to noise in the current sense circuit, due to parasitic capacitance and inductance, depending on layout, the typical culprit is switching noise from the node of Q2 drain / D2 / L1, adding a RC snubber here (parallel to D2) might help.

Cbatt should be low esr and close to the coil and sense resistor to minimise the loop area.

If you have access to a oscilloscope try to take a few measurements of the converter waveforms, this will give us some clues as to where to look further.

interesting waveforms are 

switching node
CSB
Vbat
Vin
....

Br Ton
 


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