Dynamic logic level shifting?

[5321488]

Hi,

I have a digital input that could have an anywhere from 3.3 to 12v high level feeding into CMOS logic that will run at 12v. What is the best way to convert the levels, ideally something better than a bunch of different voltage LLCs and a range selector?

Thanks!

[Ian.M]

How fast?
Is there an external reference voltage for the logic '1' level available?

[5321488]

How fast?

It needs to be able to produce a pretty much no delay square wave at max. 1kHz

Is there an external reference voltage for the logic '1' level available?

Potentially, although it could result in a range-like setting which I would like to avoid

[Ian.M]

I was thinking simple comparators, with the hysterisis feedback clamped to the (buffered) logic '1' reference voltage, so the hysterisis tracks with the reference voltage

[5321488]

As long as the waveform is the same shape, length, time etc. as input on output, any delay doesn't matter. Any comparator should do?

As above, how fast does the propagation time have to be from external high to output high, and external low edge to output low edge?

What is the specification for both high and low levels?  If the maximum permissible "low" input voltage also increases substantially as the minimum input high level does then that complicates matters more.
e.g. some arbitrary input signal interpretation specification might be :
Input is considered low when 0<= Vin <= 30% of +PSU_Voltage
Input is considered high when +PSU_Voltage >= Vin >= 70% of +PSU_Voltage
with the region between 30% and 70% of the input +PSU_Voltage being indeterminate.

On the other hand if you had a more fixed low level input range like:
Input is considered low when 0<= Vin <= 1.1V while the input high could be anywhere from say 2.7V <= x <= 12V
then the low input range would be less variable and itt would be easier to set a decision point threshold that may be fixed at some level like 1.1V independent of what the Vin high level was within the range.

If you have access to connect the input HIGH level reference e.g. a PSU voltage for the input circuit to the decision circuit then maybe you could use a window comparator circuit to do the level translation and you could use a resistive divider chain / comparator hysteresis network to set input reference level related thresholds ratiometrically relative to tttthe input reference voltage, e.g. 0-30% of Vref = LOW; 70-100% of Vref = High, input decision point is at 50% of Vref with under 20% of hysteresis.  That scheme will work fine for many cases where the high and low levels are ratiometric relative to a reference voltage and the comparator device is fast compared to your required propagation delays.

In the most flexible case you could have a Vhigh reference input as well as a Vlow reference input and set the decision points relative to those more independently though that may not be required in most cases.

You could also consider whether a series resistor (e.g. 4.7k)  and schottky small signal diode rail clamp arrangement that clamps the input high level signal excursion to the Vcc of your logic  might be enough.  That way anything higher than the VIH level of your logic gate would be seen as high and voltages up to your 12V limit would not cause the input of the logic IC to move to anything over Vcc+0.4V or so, protecting the logic input.

Hi,

I have a digital input that could have an anywhere from 3.3 to 12v high level feeding into CMOS logic that will run at 12v. What is the best way to convert the levels, ideally something better than a bunch of different voltage LLCs and a range selector?

Thanks!

I kind of understand what you are saying but probably don't have the technical knowledge to properly implement it. Are you able to post a schematic? Something with comparators and hysteresis, or with a diode clamp would be good.

I'm not sure about impedance. It probably isnt an issue.