EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: misad on December 02, 2018, 08:44:20 pm
-
Hello, I try to design a DPLL and its output successfully locked at 500Mhz. But the PFD's up signal always there and the charge pump works all the time. The very strange thing is that, the output keeps 500Mhz. I think it's because the Divde-by-10 out is always lag than the input signal. Can I do something eliminate the UP signal and make VCOin stable?
-
Disclaimer: I've only worked with analog PLLs, not DPLLs. But the mathematics are the same.
First, congratulations on a stable lock.
But it does look odd, I agree.
Normally, I'd expect the counter output (lowest trace) to align with the reference input (top trace), so divider delay shouldn't play a role in the loop.
Also, the "UP" and "DN" pulses would be aligned with the rising/falling edges of the reference input.
Is there some kind of "filter leakage" in the loop?
A block/system diagram of the PLL would help.
-
This is the block diagram of my DPLL. I don't know what's the filter leakage...
-
We need a bit of clarification: when you say "DPLL", do you mean digital PLL, as in implemented with an MCU or DSP?
-
I mean the PLL build by MOS transistors.. The Cap or the Res are all implemented by MOS transistors.
-
So it's not a DPLL, it's an analog PLL.
I suspect your HF_LoopFilter cap has a leakage to ground, which would explain your results. Try modeling with an ideal cap.
-
I use the analog Cap, but VCOin still goes up... I zoom in the output frequency waveform and see it's not exact 500Mhz. Is it possible this is because the VCO, since I use the ring oscillator, it's hard to generate a stable 2ns(period), 50% duty cycle wave...