Heh, I wouldn't trust what a PCB fab says, but a PCB assembler yes. If they do both, then that's probably fine too.
Note that spokes are hardly anything at all, thermally or electrically -- given judicious dimensions, and typical densities used in PCBs.
So what good are they in soldering? Soldering is done at much higher heat density. If the spokes drop say 1 K/W, that's inconsequential for the say 5W you might get out of a D2PAK; but if you're putting 50W into it by soldering iron, or who knows what by hot air -- now you're talking the difference between the joint reaching MP (180 to 230°C depending on alloy) or not at all (versus a cold board / no preheater, and a hot end at 200-300°C say).
And, note that hot air machines have much faster airflow than you'd normally use in a project, so of course the convective heat flux can be much higher: a D2PAK might dissipate hardly a watt over its surface in operation, at maximum temperature (minimal footprint, no heatsinking), but it can absorb enough power in this condition to make a difference (even with heatsinking pours).
As for spoke size, I would suggest maybe max(pad width, pad height) / 8 or so as a starting point, also not to exceed minimum pad width/height (shouldn't be a problem, pads aren't usually so narrow as to run into this), and no smaller than minimum trace width in the design.
Normally you'll just pick up two or three rules and let that be that. Like attached (download and rename to .RUL, then D, R, right-click list, Import Rules, Plane, Polygon Connect, OK, select file, OK).
And you can always remove thermals by setting the pad class (D, C, Pad Classes, create new, name 'Direct', add pads in list; this list will not be updated from SCH so persistent selections can be made here, but mind to check things as you add/remove/rename components).
And to be clear, for those who don't know: PCB laminate sucks thermally. It's not a terrible insulator, particularly thru-plane. Lateral is merely "not great" conductivity. Copper pours spread heat laterally (over a diffusion length on the order of 2cm/sqrt(oz of Cu thickness), something like that maybe?) so, greatly increase the dissipation of a component, going from say burning hot (150°C, no margin) for a D2PAK at 1W, to comfortably dissipating 5W (on a multilayer board). So, easily a 5x improvement. For thru-conduction, consider that, because laminate is so bad thru-plane, it pays to spread the heat out first, and then stitch it together. I mean, do both where you can, of course -- but you'll get much more heat dissipated through the laminate itself (without vias) when it's spread over a wider area. This can be good enough for a few watts on a 2-layer board without vias (topside pour only), or a 4-layer board has thin enough laminate to the nearer inner plane that the same is true for a minimal footprint. Indeed, inner planes are quite effective heatsinking, which goes for trace ampacity as well, hence why IPC-2152 asks about plane area and height.
As for thermal vias, they increase the thru-conductivity massively: a modest grid of them increases thru-conductivity by, oh I forget how much anymore, 20x or something? So, with them placed near or under the component, the hottest points can be communicated to far layers, where they are able to spread out without having to be carried through any thickness of laminate. Vias can be filled with solder for a modest ~2x improvement (less if the via is small, or plated-up copper is already fairly thick, i.e. 2oz+ inside the hole), assuming no issues from solder wicking/floating. (Fairly safe to do on D(n)PAKs I would say, but maybe worth avoiding for SON/QFN/etc.)
As for solder fill, you could get this say by using regular-dimensioned vias (i.e. normal pad size and soldermask opening), exposing the bottoms to wave soldering. Or using excess paste on the top, or paste-in-hole, so they wick up during reflow. Use modest or large size vias: 0.5mm i.d. seems a good combination of density and solderability. Conversely, to discourage solder wicking, use small (<= 0.3mm i.d.) vias, and choke down the soldermask to minimum clearance around the hole (typically 3 mil expansion from hole edge). Also, lead-free wicks less than leaded.
Note that solder-filled vias may be bumpy on the free side, which makes heatsinking more challenging. If it's the kind of build where you have passives on the bottom anyway, you'll use a one of those squishy thermal pads to smoosh around them and it's fine either way; conversely, if you're expecting to, say, stick it down with a thermally conductive self-adhesive pad, or just a much thinner (squishy) pad, or just straight up grease -- you're going to have a bad time [if the solder's sticking out].
Oh and thermals to vias: useless, turn that off (the attached rule includes this). The main exception, I would think, is if you're using them as test points, and need the thermals to facilitate soldering in debug wires -- in which case, you might consider converting them to free pads, so they dodge the rule. Or use SMT pads on whatever side is accessible, good for tacking on wires -- or probing on bed-of-nails in production.
As for placement of thermal vias: near the component. Additional stitching away from the component does very little, you've already equalized the temperatures well enough, you're hardly going to net any lower thermal resistance out there. Or put another way: the vias closest to the component are the most important, and those distant are proportionally (quadratically? exponentially?) less so. Same goes for current sharing, you aren't doing anything by using huge fucking patches of vias, you're just turning your board to swiss cheese and probably reducing overall cross section in the process. (Especially so on multilayer: mind the negative space around the vias!) Just one or two rows of vias is adequate for either purpose.
Speaking of which, I've done this before, on a multilayer design: I had power connections routed under a complex QFN (multi pad), I used a quincunx of vias per pad and set their inner-layer pads equal to diameter (Top-Mid-Bottom pad stack) so the inner polys can get as close as possible. This allowed the pours to weave inbetween, rather than be almost completely cut off by the pattern. (Note that unconnected pads are removed on gerber output, so normally the inner clearance is extra. Put another way: I'm doing that step manually to solve a tight routing issue.) (Note also, fab tolerances to inner layers are cumulative, so, fairly poor. Namely, layer registration adds with drilling tolerance. I set the inner clearance to account for this!) Finally, the vias were quite small (8 mil), and reduced soldermask clearance (i.e. to the hole edge, rather than pad edge) to avoid wicking.
Also one final note, about soldermask: either fully tent, or keep open. Partially tented, traps gas and generates voids in the solder joint. Not good. Of course, full tenting is a PITA in most any design, and sacrifices solder joint area besides -- so the preferred choice is none. That doesn't mean you need a whole pad exposed on the backside -- reduced solder mask (using expansion rule from hole edge) is a nice compromise. It's very poorly solderable (it's not likely to pick up solder during wave), and it's very unlikely to get clogged with mask. It's still not even useless as a test point, actually: for 0.5mm+ vias, you can comfortably get a wire inside, and the wire carries heat into the hole. Also, if it fills with solder due to wicking from the top side, it's likely to stick out much less (it's not forming a meniscus across the full bottom pad), making thin thermal pad / flush mounted heatsink use easier.
Tim
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