HP 4953A monitor re-use.

[RetroSwim]

Following on from my posts here: https://www.eevblog.com/forum/testgear/hp-4952a-protocol-analyzer-service-manual/

I want to re-purpose this HP 4953A protocol analyser into something cool and retro game related. I've re-furbed the PSU, mapped out the keyboard matrix, and reverse-engineered the green phosphor 9" monochrome CRT monitor. It's a fixed-sync monitor, 60Hz vertical, 25kHz horizontal. It takes +5V, +12V, and four active-low TTL-level signals, one each for H and V sync, a pixel bit, and an intensity bit. The protocol analyser's CRT2 board has a 25MHz crystal on it, so I'd say the horizontal resolution is somewhere around or perhaps just north of 650-700px viewable (allowing 200px or so for retrace, front porch, and back porch).

The 25kHz horizontal refresh is too slow to display 480-line VGA signals natively (I'll get back to this later), but should be just right for 350-line EGA signals (with room to spare). My idea is to have a small vintage PC mounted inside the chassis with an EGA card, some simple double-buffering circuit, and a microcontroller circuit to interface with the keyboard.

So my question is: Is a FPGA (or maybe a CPLD?) the right tool to build a simple TTL video double-buffering circuit? Writing to the display from buffer A while buffer B is filled, then swap and repeat, it seems simple enough, but I don't know enough about CPLD/FPGA capability to say for sure.

I've seen barebones Altera Cyclone II dev boards on DealExtreme, and now seems like as good of a time as any to learn, but I want to know if that approach is going to work before I spend a lot of time learning Verilog or VHDL.

[RetroSwim]

Well, I've made some progress. The monitor can indeed be used separately to the protocol analyzer brains.

Shown here with the CRT2 board removed for emphasis. All the protocol analyzer is doing right now is powering the monitor. Sync and the signal are being generated on an ATMega328P-PU. The code I used is geared towards a VGA monitor, so the front/back porch delays are wrong, and the text wraps around into the H retrace.



Next is do design my custom FPGA double-buffering device.