Reducing the parasitic power loss through potential divider sensing.

[Sirius631]

Hi,

I'm toying around with plans for a PWM solar charge controller, using an Arduino to sense the panel voltage and the battery voltage. Obviously, the voltages from both of these are above the input capability of the Arduino's analogue pins. I've seen others get around this by dropping the voltage using a set two resistor potential divider.

Every time a potential divider is mooted there follows the discussion of use high enough value resistor to not waste too much power, but not so high that you get noise of the PWM getting coupled back in and interfering with the circuit's operation.

The question for your consideration is this: considering that the program running on the Arduino only looks at the voltage on the potential divider output and takes action based on that reading in discrete timeframes, is there a benefit to be had in actually switching off those potential dividers by use of a MOSFET at other times? I've not seen it done before, in my limited experience. Maybe it is regular practice, or maybe it is totally impractical or just not energy efficient as I might guess.

Thoughts?

[JohnnyBerg]

Suppose the Solar panel is 245Wp and power loss in the divider is 24,5 mW, what is the point in trying to reduce that?

[Sirius631]

Suppose the Solar panel is 245Wp and power loss in the divider is 24,5 mW, what is the point in trying to reduce that?

Basically, I'm working with a 2.5W dashboard charger, so I don't have a lot to work with. Around here there's a lot of talk of marginal gains. If it saves more than it wastes, then it's a good start.

[Moseven]

It is not practical to turn on and off a voltage divider.

The Arduino input has an impedance of 100M or more. However, the ADC requires an impedance of 10k or lower, since the ADC needs some current during the analog-to-digital conversion.

You could for example try 1M and 47k resistors. The impedance of the circuit will be around 47k, so perhaps you don't get the full 10-bits accuracy. Select a low internal reference voltage. And use the average of few samples.
Or even better is adding a capacitor next to the 47k. That capacitor keeps the voltage stable during the analog-to-digital conversion. I can be 10nF to 100nF, or something like that.

To measure 12V, I would use: 1M, 47K, analogReference() of 1.1V, 100nF.

[georges80]

A pwm charge controller for a 2.5W panel... Is this for topping up the car battery or ?

cheers,
george.

[Ian.M]

It depends on the battery capacity and technology.  If your voltage sensing divider takes an order of magnitude less current than the battery's expected self-discharge rate (which varies from 1%/month for LiPO under ideal conditions to >>20%/month for NiCd or Lead acid at elevated temperatures, there is no benefit whatsoever in reducing the sensing current.  e.g. a 100AH Lead Acid deep cycle battery can be expected to discharge at typically 5%/month.  That's 5Ah in 30 days or 7mA.   Get the sensing current down to 1mA and forget about it!

High side MOSFET switching makes sense when you are dealing with smaller LiPO batteries or primary cells.   The self-discharge rate can be very low and you dont want  extra standing discharge with the equipment off or in standby as it will kill the batteries in storage (especially LiPOs that are initially nearly fully discharged).

Most microcontroller ADC inputs have quite stringent source resistance limitations.  If you add a low voltage single supply micropower CMOS rail-to-rail OPAMP operating off the microcontroller's Vdd rail, configured as a unit gain buffer, it makes the design much easier as the OPAMP will have no problems with a source resistance of hundreds of K while providing a low impedance signal to the the ADC.

You only get noise pickup if your layout is poor.  Use a ground plane and guard tracks and you can get totally reliable results with a 1M source resistance into a unit gain buffer, though some care to roll-off the HF performance (such as a small capacitor from the divider tap to ground, chosen to have a time constant with the Thevenin resistance of less than the interval between samples) is needed if you don't want it to freak out if you bring a strong RF source lke a mobile phone near it.

[JohnnyBerg]

Basically, I'm working with a 2.5W dashboard charger, so I don't have a lot to work with.

That wasn't in the original post 

I have a battery powered Arduino, and turn off the reference and divider when the Arduino goes into sleep mode. (current draw is then 160 nA)
I use 2 mosfet's  (2N7002 and AO340) and a 100k ohm resistor  to get the job done.  I suppose you could do the same.

[Sirius631]

A pwm charge controller for a 2.5W panel... Is this for topping up the car battery or ?

cheers,
george.

It's more experimentation  at the moment for another. larger panel. The last time this panel was on a car, Dad trapped the cable in the hood, shorted it and set the car on fire, so it's not going anywhere near my car.

[Sirius631]

I have a battery powered Arduino, and turn off the reference and divider when the Arduino goes into sleep mode. (current draw is then 160 nA)
I use 2 mosfet's  (2N7002 and AO340) and a 100k ohm resistor  to get the job done.  I suppose you could do the same.

Yeah, I haven't got a low power Arduino, just the regular Duemilanove, Uno and five Nanos. I suppose a 3.3v type should be on the cards for this project if I'm really worried about power usage. My approach to these things is to purposefully give myself problems and find work-arounds before being forced to spend any more money. As they say, "necessity is the mother of invention".

I can get 20v off the unloaded panel. Obviously, that will drop once it's got a circuit attached. If I accept the high resistance = high noise scenario (ref Afrotechmods video) and go for lower value resistors in a potential divider, I'm getting 9mW of power wasted in the divider using 10k & 33k. I suppose 100k and 330k aren't too scarily high. I see y

I suppose I should just suck it and see. I can always come back to the switched divider idea if I'm feeling masochistic. I'll investigate further about the source impedance into ADC input; I do see how Ian.M's suggestion of a unity gain op-amp would work there.

[suicidaleggroll]

Sure you can switch it off, it's done all the time.  A simple high side switch with a P/N mosfet combo is cheap and easy to implement with one GPIO and will cut your current draw to nil when you're not using it.

[dannyf]

is there a benefit to be had in actually switching off those potential dividers by use of a MOSFET at other times?

It can be done.

But unless you are dealing with something really low power, it has limited benefits. Your signal source voltage isn't going to change quickly so high resistance dividers may be all you need.

Another approach is to use a capacitor - think of a capacitor as a "timed" switch.

[Sirius631]

Sure you can switch it off, it's done all the time.  A simple high side switch with a P/N mosfet combo is cheap and easy to implement with one GPIO and will cut your current draw to nil when you're not using it.

Can you give an example of the power being removed from the potential divider leg on such a frequent basis? Everyone else around here seems to not know of this technique in practice and thinks it's of little benefit.

[wraper]

Sure you can switch it off, it's done all the time.  A simple high side switch with a P/N mosfet combo is cheap and easy to implement with one GPIO and will cut your current draw to nil when you're not using it.

Can you give an example of the power being removed from the potential divider leg on such a frequent basis? Everyone else around here seems to not know of this technique in practice and thinks it's of little benefit.

Of course there is little benefit + mosfet will introduce some additional error (negligible for 10 bit ADC). What you need is just high resistance divider, + 10nF-100nF capacitor on the ADC pin. And don't sample too often or it will introduce voltage drop on the capacitor = error. Anyway running ADC all the time will cause more current consumption than divider itself.

[wraper]

BTW except of being unnecessary complicated, two mosfet circuit will also have a drawback as a significantly more current consumption when being open because of the gate discharge resistor in the high side mosfet driver. But if that resistor does have very high resistance, that would make this circuit very slow in switching.

[JohnnyBerg]

Can you give an example of the power being removed from the potential divider leg on such a frequent basis? Everyone else around here seems to not know of this technique in practice and thinks it's of little benefit.

From my NanoLipo:
(forget the reference)

[suicidaleggroll]

The diagram posted by JohnnyBerg gives the basic idea.  If the MCU has an internal reference then the 1k/zener/A6 part of the circuit can be removed as well.

Yes a large resistor divider and a capacitor can be used to reduce power consumption as well.

Switching the voltage divider on and off is good for low and very low sample rates, not so much for fast sampling because of the power lost in charging/discharging the FETs, the gate resistors, and the switching times.

Using high value resistors with a capacitor is good for medium to low sample rates, not so much for very low sample rates due to the constant current draw, and not so much for high sample rates due to the low pass filter it creates.

As with everything else in this field, whether or not either approach is appropriate depends on the application.

[Ian.M]

It also has issues with the ADC input leakage current.   While a capacitor of value 2^(N+1)*Chold (assuming a capacitive SAR ADC with Chold being its internal sampling cap and N its no. of bits)  is a valid way of getting the input voltage change due to the sampling current below 1/2 the LSB voltage step, when you consider the datasheet worst case input leakage current multiplied by the Thevenin resistance of the divider, you will see that for high resistance dividers its possible to have a significant and unpredictable error.

There is *NO* substitute for an OPAMP buffer when driving a MCU's integrated ADC from a high impedance source.  The OPAMP doesn't have any digital sections so can be optimised for good analog performance with low leakage current and its input protection is not so critical: e.g. good rail-to-rail OPAMPs frequently have operational input voltage ranges extending 0.5V or so outside the rails so that simple Schottky clamping is effective if the source resistance is high enough, and worst case, its only that chip's output that is disturbed but if you let current flow through the internal protection diodes on an analog input of a MCU, it can disturb other ADC channels and even seemingly unrelated on-chip modules such as band gap references, brownout detection circuits clock oscillators and watchdog timers.

[wraper]

It also has issues with the ADC input leakage current.   While a capacitor of value 2^(N+1)*Chold (assuming a capacitive SAR ADC with Chold being its internal sampling cap and N its no. of bits)  is a valid way of getting the input voltage change due to the sampling current below 1/2 the LSB voltage step, when you consider the datasheet worst case input leakage current multiplied by the Thevenin resistance of the divider, you will see that for high resistance dividers its possible to have a significant and unpredictable error.

There is *NO* substitute for an OPAMP buffer when driving a MCU's integrated ADC from a high impedance source.  The OPAMP doesn't have any digital sections so can be optimised for good analog performance with low leakage current and its input protection is not so critical: e.g. good rail-to-rail OPAMPs frequently have operational input voltage ranges extending 0.5V or so outside the rails so that simple Schottky clamping is effective if the source resistance is high enough, and worst case, its only that chip's output that is disturbed but if you let current flow through the internal protection diodes on an analog input of a MCU, it can disturb other ADC channels and even seemingly unrelated on-chip modules such as band gap references, brownout detection circuits clock oscillators and watchdog timers.

Therefore I said:

And don't sample too often or it will introduce voltage drop on the capacitor = error. Anyway running ADC all the time will cause more current consumption than divider itself.

If sampling will occur only occasionally, then there will not be significant average leakage current and capacitor will have enough time to recharge between sampling times.

[Ian.M]

No.  input LEAKAGE current which is present all the time, not sampling current which is only present when the sampling switch (transmission gate) is closed.

Consider a 10 bit ADC, with 2.048V Vref.  The LSB represents a voltage step of 2mV.  1uA through a source resistance of 2K will give you that much voltage offset so if the worst case input leakage current is 1uA (not uncommon at the upper limit of a MCU's temperature range) you need to design your ADC circuit for 1K source impedance to maintain +/-1/2 bit accuracy.

N.B. I missed some brackets in the expression for the input cap: Cext>=(2^(N+1))*Chold

[Sirius631]

Can you give an example of the power being removed from the potential divider leg on such a frequent basis? Everyone else around here seems to not know of this technique in practice and thinks it's of little benefit.

From my NanoLipo:
(forget the reference)

Yeah, that's kind of what I was thinking. So it's been done before, for the same reason. Well, nobody can accuse me of being original. 

[Siwastaja]

Can you give an example of the power being removed from the potential divider leg on such a frequent basis? Everyone else around here seems to not know of this technique in practice and thinks it's of little benefit.

I do it in a battery management system, where every single li-ion cell powers a microcontroller. I don't use a separate MOSFET, but just an IO pin directly on the low side. The arrangement is:
Vcc --- 470R --- ADC input --- 120R|100nF --- IO pin. Low resistor values provide good noise margin and low impedance for the ADC, as well as quick charging of the filter cap (which also helps with the impedance). There is a 5 ms delay after powering the divider so that the capacitor is charged.

The IO pin trick does add a source of error that isn't negligible, but everything is software-calibrated anyway with offset, gain and temperature compensation (the MCU has an internal temperature sensor).

Quiescent current consumption less than 50 µA was an important design goal, and this was the easiest way to achieve it - with zero extra components. This is the simplest distributed cell-level BMS with the smallest BOM I can imagine, and  the specs are still quite good.

I guess I could have done it with high enough divider values to obtain < 50 µA divider current, and then just use large enough cap (100 nF probably OK) to filter any noise and provide the low-impedance source for the ADC. On the other hand, the switchable low-resistance network provided me an alternative way to burn excess charge (cell balancing) without extra components.

[suicidaleggroll]

I do it in a battery management system, where every single li-ion cell powers a microcontroller. I don't use a separate MOSFET, but just an IO pin directly on the low side. The arrangement is:
Vcc --- 470R --- ADC input --- 120R|100nF --- IO pin. Low resistor values provide good noise margin and low impedance for the ADC, as well as quick charging of the filter cap (which also helps with the impedance). There is a 5 ms delay after powering the divider so that the capacitor is charged.

The IO pin trick does add a source of error that isn't negligible, but everything is software-calibrated anyway with offset, gain and temperature compensation (the MCU has an internal temperature sensor).

Quiescent current consumption less than 50 µA was an important design goal, and this was the easiest way to achieve it - with zero extra components. This is the simplest distributed cell-level BMS with the smallest BOM I can imagine, and  the specs are still quite good.

I guess I could have done it with high enough divider values to obtain < 50 µA divider current, and then just use large enough cap (100 nF probably OK) to filter any noise and provide the low-impedance source for the ADC. On the other hand, the switchable low-resistance network provided me an alternative way to burn excess charge (cell balancing) without extra components.

That will only work when the MCU is measuring its own power supply.  If it's trying to measure a voltage higher than its own Vcc (such as what the OP is trying to do), that approach is both pointless and dangerous (for the MCU).  When you lift the GPIO high, that will raise the ADC input voltage above Vcc, causing it to dump current through the ADC pin's protection diode.  With a more reasonable voltage divider it would simply waste power, but with those values it could easily latch up the MCU or burn out the pin.

That voltage divider will also likely result in significant error due to the MCU's output resistance when it tries to sink it to ground.  You said you're calibrating that out, but that just seems like a big fuss for no benefit.  Why bother with having to derive and apply a full temperature calibration when there are so many easier ways to do this that don't suffer from that problem?

I'm not really understanding the point of the 100nF cap either, or the 5ms delay.  The Thevenin equivalent output resistance of a voltage divider is the parallel combination of R1 and R2, in your case 95.6 ohms.  With a 100nF cap that gives you an RC time constant of 9 uS and a corner frequency of over 15 kHz, so it's ready to sample in about 100uS and it's not doing much filtering anyway.