variable frequency square wave

[NorthGuy]

Requirements are clearly stated in the OP: "0.1% accuracy of the frequency control".

If only the frequency must be accurate, then many MCUs have NCO or DCO peripherals which can generate frequency very accurately, at the expense of higher jitter.

[ogden]

Requirements are clearly stated in the OP: "0.1% accuracy of the frequency control".

If only the frequency must be accurate, then many MCUs have NCO or DCO peripherals which can generate frequency very accurately, at the expense of higher jitter.

Those usually are kinda fractional frequency dividers, right? Yes, that's option indeed - in case jitter of +/- clock cycle (of divider) is acceptable.

[IDEngineer]

Divisor 59,234,757 to get what exactly??? 72000000/59234757 =1.2155 Hz. It is way off 993000 Hz I asked for.

OMG. 

I'll try one more time.

Your 72MHz clock scaled by 32 bits yields an LSb of 0.017Hz. Your desired frequency of 993KHz means you need (993000 / 0.017Hz) LSb's. Do that equation and see what number you get. Then calculate the error of that "missing" 0.3 LSb.

EDIT: I just know you're going to freak out over your answer being different than the number I gave. The reason is because my number comes from doing precise math, while in my equation above I rounded the value of the LSb. The exact equation is:

     (993000 / (72^06 / (2^32)))

...which yields my earlier value.  QED. 

[ogden]

Divisor 59,234,757 to get what exactly??? 72000000/59234757 =1.2155 Hz. It is way off 993000 Hz I asked for.

OMG. 

I'll try one more time.

Your 72MHz clock scaled by 32 bits yields an LSb of 0.017Hz. Your desired frequency of 993KHz means you need (993000 / 0.017Hz) LSb's. Do that equation and see what number you get. Then calculate the error of that "missing" 0.3 LSb.

EDIT: I just know you're going to freak out over your answer being different than the number I gave. The reason is because my number comes from doing precise math, while in my equation above I rounded the value of the LSb. The exact equation is:

     (993000 / (72^06 / (2^32)))

...which yields my earlier value.  QED. 

LOL.  No horses were harmed in this most ridiculous calculation of frequency division, ever. Do you even know how timer peripheral or any other discrete frequency divider works? BTW I did provide hint for you, "Hint: 72MHz divided by 72 is 1MHz but divided by 73 is... 986 KHz which is 0.68% away from 993 KHz."

[IDEngineer]

Anyone else want to try explaining prescalers to this guy? I've taken my turn in the barrel, ready to sit back and  .

[ogden]

Anyone else want to try explaining prescalers to this guy? I've taken my turn in the barrel, ready to sit back and  .

Prescaler of stm32 timer is just clock divider. It can divide clock (and obviously frequency) by integer number. In frequency generation applications timer is integer divider as well. Your math of frequency dividers from alternate universe contains multiplier 

EDIT: I just know you're going to freak out over your answer being different than the number I gave. The reason is because my number comes from doing precise math, while in my equation above I rounded the value of the LSb. The exact equation is:

     (993000 / (72^06 / (2^32)))

Fact that you are able to write equation does not mean that timer is able to operate accordingly

[mark03]

Guys...  (assuming you are both guys due to the apparent fragility of egos!)

I think a bit of reflection will show that the frequency resolution of any MCU timer-based divider scheme is



(In other words, @ogden is correct.)

It's too bad there is so much noise in this thread because the underlying question is actually very interesting.  I posed a similar question a while back (https://www.eevblog.com/forum/microcontrollers/square-wave-synthesis-with-high-frequency-resolution/msg897489/#msg897489).  The boring answer is "just use a DDS and square-up the sinusoid" but there are applications where it would be really nice to do all of this inside an FPGA.  I still intend to look into this further, although that project is clearly on the back burner---the thread is more than three years old!!

I wish there were a nice technical write-up on the design of the Si5351, describing how the topology was chosen, how it works, the key technical challenges and how they were solved, etc.

[NorthGuy]

Requirements are clearly stated in the OP: "0.1% accuracy of the frequency control".

If only the frequency must be accurate, then many MCUs have NCO or DCO peripherals which can generate frequency very accurately, at the expense of higher jitter.

Those usually are kinda fractional frequency dividers, right? Yes, that's option indeed - in case jitter of +/- clock cycle (of divider) is acceptable.

Since jitter is not specified, then obviously any jitter is acceptable. Otherwise, you need to have full specs first - jitter, rise/fall times, distortions - everything which is needed for the applications. Then you can think of the best method. It is silly to design something without specs, then rejects it because it doesn't meet unspecified specs.

[Kleinstein]

Requirements are clearly stated in the OP: "0.1% accuracy of the frequency control".

If only the frequency must be accurate, then many MCUs have NCO or DCO peripherals which can generate frequency very accurately, at the expense of higher jitter.

Those usually are kinda fractional frequency dividers, right? Yes, that's option indeed - in case jitter of +/- clock cycle (of divider) is acceptable.

The NCOs are more like DDS related, counting up the phase at a given rate and than directly give out the upper bit. Fractional dividers are similar, but updating the adder at a variable rate, set by the integer divider part.  So the jitter is essentially the same, just a different control and implementation.

[ogden]

I wish there were a nice technical write-up on the design of the Si5351, describing how the topology was chosen, how it works, the key technical challenges and how they were solved, etc.

Si5351 is nothing special. PLL+VCO with 600-900 Mhz range and dividers. Such clock generation approach is widely used since yr 1970 or so. Perhaps TI have more info in their documentation of clock IC's http://www.ti.com/product/CDCE913