Hi!
I am currently working on a project, which should have an AES3 input (the professional balanced version of SPDIF). But I haven't found much info about how to design a proper transformer isolated input and the differential receiver.
The requirements are: support both 48 and 96kHz audio stream, that is up to 12mbps data. (SPDIF bit rate is 128*fs)
I have tried my best to find a
suitable transformer, which would not cost a fortune and would be easily available. Meh.. I couldn't find almost any, which would be rated at the double sampling 96kHz (12Mbaud).
The only one available I have found is
Pulse PE-65612 (PE-65812 respectively). But it is rated only up to 7Mbaud with 25ns risetime (not good enough I think). God knows if it will run at the double sampling rate, at 12Mbaud. It is almost twice its rating. The datasheet is attached. What transformer would you suggest to use?
It is quite difficult to find one with high primary inductance (1mH+). Those ethernet transformers, which are quite cheap and fast enough have mostly only 300uH primary inductance and I quite unsure how those will handle the AES3 voltage levels at lower samplerates (i.e 6Mbaud only at 48kHz). I don't think it is a good idea to use one of these either. Dead end. What transformer should I use? What do you recommend?
The
differential receiver. I have read several times on several places, that RS422/485 line receivers may be used for the AES3. But the old good SN75176B is only up to 10Mbaud. Too slow. And I couldn't find a better one. Some parts from LTC popped up, but those were mostly 0pcs in stock or expensive as hell. Do you have any experience or can you suggest a cheap differential line receiver usable together with the AES3 bus? I need a CMOS 3.3V level on the output.
The circuit I could come up with is this one
attached. R36-37-38 is an optional voltage divider (let's say its sole purpose is for experimenting with transformers), should be omitted. R39 is the termination resistor. The AES3 line should have 110ohm impedance (the transformer is 1:1 ratio). R40-C70 is a kind of impedance correction/equalization circuit I have seen somewhere used, but couldn't figure out how did they obtained the correct values. The R was some hundred ohms and the cap some puff. Is this circuit a correct approach?
How should I interface the secondary side of the transformer to the line receiver (like 75176)? Probably have to be biased, not left floating. Maybe divide the termination resistor in half, couple the center to ground with a 100n cap and bias it with half the receivers input range/supply.
Thank you for suggestions, this is my first SPDIF/AES encounter.

Yan