proper FET switch design does contain a gate resistor to limit the charging current spikes and eliminate or minimize ringing in the drain circuit. Heavily overdriving the gate usually results in oscillations in the MHz to GHz range subject to details of the circuit. You don't necessarily want that.
On the other hand, a gate resistor can also result in the FET spending much longer in between the fully-on and fully-off states than it could do, resulting in a huge increase in switching losses. A couple of misplaced ohms here can be the difference between a switch that works well and gets a bit warm, vs one which overheats and lets the magic smoke out within seconds of being switched on.
I use power MOSFETs in dc/dc converters a lot; normally the problem is turning them off and on fast enough.
Limiting the gate charge/discharge currents will slow down FET turn-on and turn-off, that much is true.
Whether this has an impact on performance and what kind of impact, is a topic for circuit analysis and design in each case, there is no single right answer.
So far we have been discussing the so called hard-switching case where the FET switches full drain voltages and currents simultaneously. I attached a diagram i have made some time ago, outlining the normal turn-on sequence of a hard switched FET. You can see that the full drain current has developed before any appreciable decrease in drain-source voltage Vds. During this time the device will dissipate almost full Vds x Id, emphasizing the need for rapid switching.
In practice there is always a "gate resistor" of some kind, if only the source impedance of the output feeding into the gate and parasitic impedances of the actual circuit. Often this impedance is low causing the gate to be heavily overdriven. Now a small/reasonable amount of overdrive is desirable to account for component parameter variations and to ensure full switching. Gross overdrive will result in oscillation of the drain circuit, sometimes severely.
The idea to optimally drive a FET gate is to provide the electric charges Qgs and Qgd in minimum time to ensure a quick turn-on of the main channel and vice versa. Once that is done, further driving the gate will result in overcharge. Since the channel is already fully on, no further increase in conduction is possible.
A practical first approximation in designing the gate circuit would be to consider the required switching time and gate charges (yes - charges, NOT capacitances. The capacitances vary as a function of the drain-source voltage). So do the charges of course as functions of Vgs but those are usually available in the datasheets. Lets take an example, say the regular run of the mill IRF540N that we have learned to trust and love. Say you want to turn it on and off in 1 microsecond (let's be reasonable here, this is an older spec component). From the IR datasheet you can see that assuming our Id would be say 20A max, the device will be fully on when Vgs => 5V. Lets use a comfortable margin and say we drive the FET with a gate voltage of 8V. Further checking the datasheet we see that the total gate charge at Vgs=8V will be around 35-38 nC subject to Vds. Lets use 38 to be on the safe side and now we can right away calculate, that to transfer 38 nC of charge in 1 us, we need 38 mA of current. Next, again checking the gate charge vs Vgs diagram we see that the plateau t2 - t3 occurs at around 4.5V Vgs. This is the voltage available to drive the turn-on current. Now, simple division gives us R = 4.5V / 38mA = 118 ohms. This is the first approximation for the gate resistor.
Further complications may require that the charge and discharge currents be made unequal and then the next step is to add series diode-resistors in antiparallel to control the gate resistance in both directions separately. After that it gets more complicated and laziness prevents me from going there in this post.
So, while overdriving a FET gate to the max does result in the shortest switching time, you don't usually want the side effects that the high dv/dt and resulting displacement currents bring. In a straightforward hard-switching case the reasoning i outlined above should be applied and if not good enough, improved designs should be considered. A better controlled gate charging circuit may be used, or one can try to suppress the ringing resulting from overdriving. Or finally a more clever switching strategy could be attempted such as a ZVS scheme or synchronous/resonant switching, avoiding the hard switching issue altogether.
Meanwhile the attached IR app note clarifies my point in some more detail.