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Trouble with Transmission Gates....
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SiliconWizard:
You should consider implementing your FF without pass gates.

Something like: https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#/media/File:True_single-phase_edge-triggered_flip-flop_with_reset.svg
?

Note that this is a dynamic FF here, so this is a bit of cheating. Dynamic logic is an interesting tool to know, but it has drawbacks. It requires constant clocking.

A typical static D flip-flop will look like this: https://en.wikipedia.org/wiki/Flip-flop_(electronics)#/media/File:Edge_triggered_D_flip_flop.svg
(That's 6 NAND gates with one with 3 inputs, so that would be 25 transistors.)

The master-slave configuration: https://en.wikipedia.org/wiki/Flip-flop_(electronics)#/media/File:D-Type_Flip-flop_Diagram.svg
(8 NAND gates, two inverters: that's typically 36 transistors.)

So unless you're going for a dynamic version, not quite "cheap"!
BurnedResistor:
I did see that image floating around but I have no idea how that is supposed to work   :scared:

I kinda don't want to blindly implement it without understanding it - the whole point of doing this from the transistor level up was to try and understand as much of it as possible :)

Ill try and see if I can learn anything more about it (Some basic googling seems to refer to it as C2mos?)
SiliconWizard:

--- Quote from: BurnedResistor on February 23, 2020, 05:04:12 pm ---Ill try and see if I can learn anything more about it (Some basic googling seems to refer to it as C2mos?)

--- End quote ---

Yes, this is dynamic logic, also sometimes called "Clocked CMOS logic" when it's implemented with CMOS.
You can find lectures about that out there.

As I said, one drawback is that it can't operate statically.
Benefits are several including lower transistor count, and in many designs in which the clock "never stops", they are a good fit. They'll be of course a problem if you need static operation (such as retaining state when the clock stops.)


BurnedResistor:

--- Quote from: SiliconWizard on February 23, 2020, 05:26:48 pm ---
--- Quote from: BurnedResistor on February 23, 2020, 05:04:12 pm ---Ill try and see if I can learn anything more about it (Some basic googling seems to refer to it as C2mos?)

--- End quote ---

Yes, this is dynamic logic, also sometimes called "Clocked CMOS logic" when it's implemented with CMOS.
You can find lectures about that out there.

As I said, one drawback is that it can't operate statically.
Benefits are several including lower transistor count, and in many designs in which the clock "never stops", they are a good fit. They'll be of course a problem if you need static operation (such as retaining state when the clock stops.)


--- End quote ---

I will get to work!

Thank you :)
SiliconWizard:
If you don't know her already, Jeri shows the concept in a simple way with some experiments:


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