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Trouble with Transmission Gates....
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BurnedResistor:
Hey All!

After taking a class in Digital Electronics I wanted to construct a D-FlipFlop with CMOS tranmission gates.
I had seen basic CMOS logic gates in the past but had never worked with tranmission gates.

I constructed the following Transmission Gate for testing:



Using BSS84 2n7002 Fets.

I am not able to get the gate to work. As far as I understand, if I Enable the Control signal (Ctrl = 5V, !Ctrl = 0V)
the gate should be able to conduct in both directions between A and B.

If I apply 5V to the B terminal, and connect A through a resistor to GND I am able to pull current from B to A only when
the gate is enabled - as expected.

However, if I connect 5V to A, I can draw current from B no matter what the CTRL signal is at.


I have also attempted to construct the gate by having the drains and sources of the fets connected to each other instead of
the Source-Drain Connections I have drawn above, but then the gate conducts in both directions no matter what the control signal is.
Hey, at least it is parallel?  :-//

Anybody got any idea what is going on here? I am at a loss.
Wrong Transistors? Am I misunderstanding something?
(Could cheap transistors from LCSC.com be the cause?)

Thank you!
BurnedResistor:

--- Quote from: blueskull on February 23, 2020, 02:05:37 pm ---For vertical MOSFETs, there is a body diode allowing current to flow from the "nonintended" direction without control.

For an NFET, you normally would expect it to block from drain to source, so the body diode allows uncontrollable flow from source to drain.

And vice versa for PFETs.

--- End quote ---

That makes a whole ton of sense, and explains all the behaviour I was seeing.

(Who would have thought that the diodes included in the Mosfet-Schematic symbol are not just there to look fancy  :-// )

Thank you for the fast response.
BurnedResistor:
Thank you for the detailed explaination!
SiliconWizard:
Yep, body diodes!

Don't feel bad, this is a common trap. Unfortunately, if you're using discrete transistors, you will have a hard time doing what you want to do here.

If you'd really like to prototype something with discrete parts, you may be able to devise something using a back-to-back configuration, using 4 transistors instead of 2.
If you don't know what I'm talking about, see the idea here for instance: http://www.ti.com/lit/an/slva948/slva948.pdf
BurnedResistor:

--- Quote from: SiliconWizard on February 23, 2020, 04:21:20 pm ---Yep, body diodes!

Don't feel bad, this is a common trap. Unfortunately, if you're using discrete transistors, you will have a hard time doing what you want to do here.

If you'd really like to prototype something with discrete parts, you may be able to devise something using a back-to-back configuration, using 4 transistors instead of 2.
If you don't know what I'm talking about, see the idea here for instance: http://www.ti.com/lit/an/slva948/slva948.pdf


--- End quote ---

I wanted to try and build a Discrete D-FF:


Another option would be to build an SR-Latch from 2 Nand Gates (8 transistors)
I could then turn that into a D-Latch using 2 Nand gates and an inverter
Two of those + inverter(s) puts me at a D-FF and about 70 transistors.
That seems a bit exessive. Especially because I was toying around with the idea of building some simple logic circuit/state machine from transistors for the fun of it.
70 Transistors per D-FF would be an issue   ::)


actual symmetrical two-way transmission isn't really necessary: The transmission gates are only used to either close the memory loop, or break the loop and connect it to the input.

I guess I could look at Tristate buffer designs?
https://electronics.stackexchange.com/questions/273933/3-state-buffer-mechanism?rq=1

Then I would only need two extra transistors per transmission gate, so I could probably do a D-FF with:

4 Not Gates (Memory Loops) = 8
2 Not Gates (Control Signal)  = 4
4 Tristate-Buffers                  = 16

28 Transistors. Still much but plausible.

(Plus if I was latching multiple D-FF in parallel as in a basic state machine I would not need individual control-signal inverters for each gate)

Or is that also not plausible?

 :P

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