Twin tub isolation on P substrate

[blueskull]

Hi all,

1. Can the bulk pin of a NMOS in a P well be connected to its source pin in a twin tub process? If I did that, won't the P substrate be shorted to the source of the NMOS?
If I recalled correctly, P well is ohmic connected to P substrate, so the bulk of a NMOS in a P well should be at zero potential all the time, otherwise there will be huge current flowing through it.
I saw this in the book "Micro CMOS Design" published by CRC, written by Bang-Sup Song, chapter 2.

2. Also, as I read through CSMC's 0.5um MS process datasheets, I found that they say I can construct a diode using N+ and P well. Won't the anode be shorted to the P substrate?

I'm a new comer to IC design, so please don't hesitate correcting me.




Thanks,
Bo

[Chris Jones]

I don't know about the process you are using, but I have worked on a process which had P-wells inside N-wells, and the inner p-wells were separated from the substrate by a buried N-layer. That enables, for example, nmos source followers that don't suffer reduced gain from the body effect, because you can tie the backgate to the source if you want. It is a while since I did any chip design so I am forgetting the details now.

If your process documentation shows a cross-section through a nmos inside a p-well inside a n-well then that should explain the situation. If you can't find such a diagram, maybe you can ask for one. I think it would be a really worthwhile thing to have.

Chris