ESD protection technical question

[croyleje]

Hello everyone,
I have read most of the post about ESD protection and spark gaps but I have been unable understand why these spark gaps work to protect the inputs of an IC.  See the attached pictures if you got a transient of some kind weather it be an ESD discharge or gross overload of some type isn't the whole PCB trace going to be at that potential voltage so how is that not going to effect the IC?  I would think that within the chip there most be areas were the distance between the input and some path to ground is closer then the gap on the spark gap ie. bond wires or internal traces/connections?  Would it only be the input impedance that save it or am I missing something?  Sorry if this is a stupid question but it just doesn't seem logical to me.
Thank you
Jason

[bobcat]

It works because when the input voltage rises above the voltage of the ESD device, the resistance of the ESD device drops dramatically. It creates a short to ground. The voltage getting to the IC is much reduced.

[alank2]

What does the back and forth snaking in the red circle do?

[croyleje]

the back and forth snaking just gives multiple places to arc over.

[croyleje]

i get that much bobcat but until the arc is established the device will be subject to hundreds of volts so wouldn't the IC be destroyed before the arc happens?

[alank2]

the back and forth snaking just gives multiple places to arc over.

How is it going to arc over when there is soldermask in that area?

[croyleje]

i believe that is just an oversight or poor design in my research though i have seen that method used widely and pictured in most design articles.  and it would arc over with the solder mask but would be much harder to determine breakdown voltage and would leave carbon traces much more easily then not having the mask.

jason

[bobcat]

Every conductor is really an RLC network with a time constant. So, voltages further down the line rise more slowly than near the ESD device. That is why it is important to have the ESD device as close as possible to the voltage source. An ESD device right next to an IC is almost useless. The high voltage must rise fast for the protection to work. A slowly rising spike or over voltage will usually damage a chip.

[extide]

Red circle looks like guard tracks to me, not a spark gap. Where as the blue circle is a spark gap.

[croyleje]

thank you bobcat that makes more sense these gaps are for fast transients ie. ESD and the other protection devices such as MOVs or PTCs would give you the needed protection for shorts or gross overloads. 
Jason

[T3sl4co1l]

Since we're talking ESD that occurs in nanoseconds, the impedance of a few centimeters of trace isn't very much.  A spike of ~2000V (guaranteed by the spark gap) will therefore appear along most points of the trace.  Proper surge arresting requires impedance along the trace, in addition to multiple protection measures.

Tim

[croyleje]

Tim that is what originally started this whole thread it just didn't make sense to me your going to end up with ~2000V on that trace and wouldn't that just blow the ass out of what ever your trying to protect?  Unless the impedance of the IC is going to save it until the arc is established those along the energy a path to ground other then via the item we are protecting?  Well thank you everyone for the info I do appreciate it.
Jason

[T3sl4co1l]

Lesson being, not every PCB designer is an expert, in fact, in my experience almost none of them are.

Tim

[Charles Creations]

Red circle looks like guard tracks to me, not a spark gap.

What if the red circle's only purpose is to increase the impedance between the IC and the input. This would just further decreases the rate at which the voltage rises at the IC's pins, so the spark gap has more time to arc over.

[T3sl4co1l]

Not enough to matter; the electrical length is maybe a cm.

Structures like that are often used for delay matching in high speed circuits, though more commonly in a microstrip format, not CPW (which has somewhat poorer signal quality, but makes up for it in saved layout area).  Obviously, in circuits where picoseconds matter.  The ESD appearing sooner or later by a fraction of a nanosecond won't make any difference to the voltages and currents in circuit; you'd need over a meter of transmission line (trace or cable) to make a dent in it.

Tim

[penfold]

You've got to remember that sometimes PCB designers don't necessarily understand what they are doing.  If i spend a lot of time on the actual circuit design I might blunder through the PCB and do a very belt and braces approach just because I don't have the time to calculate whether I actually need something or not.

Those things in the red circle could be a mistake where they meant to remove solder resist, they are unlikely to be an effective capacitance with such little impedance running towards them and an equally poor series inductor.  I think you'd have to ask the designer

With an ESD you want the source point to be as removed (via series resistance and parallel capacitance) from the sensitive point.  This has the tendency of making the pulse a marginally lower voltage and longer duration, which may not be sufficient to trigger ESD protection as fast as you'd like further down the line and is a much worse situation for the input.  In a zener style esd diode, the capacitance to ground will buy you some time and absorb a lot of the fast edge whilst the diode breaks down especially since in most cases you might not want to add any further capacitance.  Without the fast edge, you might still get a peak before the diode acts properly.

The first line of defense should be something along the lines of a spark gap, which will have a high and relatively deterministic breakdown voltage (relatively deterministic when compared with the actual voltage and source conditions of an ESD) and should have the lowest possible series resistance to the source.  Then the designer can start to consider what other measures he can take, which now that they can bit more sure on the characteristics of the ESD down the line (voltage and impedance sort of assured by the spark gap) then they can start using some capacitance and resistance to control the shape which can sort of be optimized for a semiconductor protection device, which can be better specified with almost a knowledge of the characteristics and the fact that most of the trouble has been removed via the spark gap (or alternative first line of defense)

[T3sl4co1l]

You've got to remember that sometimes PCB designers don't necessarily understand what they are doing.

True of anyone doing anything.  People in general tend to cultivate a very strong sense of personal knowledge, rarely understanding the uncertainty or outright error in their sources!  Just because "that's how me mum taught it!", doesn't make it right in an absolute sense.

Not that most subjects have an objective, rational sense of right or wrong, but engineering at least covers some rather more technically inclined arts, and allows at least some objectivity.

In this case, even without complete theoretical knowledge of electromagnetism and transmission lines, we can do some very useful SWAGs of impedance, time delay and so on.

A transmission line of that shape is probably in the 50-100 ohm range (typical of wide format CPW in two layers).  It's maybe 2" long, or ~200ps.  So for frequencies below 1GHz, it looks like an lumped inductor (circuit impedance < 50 ohms) or capacitor (circuit > 100 ohms).

ESD protection will look on the order of a few ohms when active, so that bit of trace (which is a transmission line, whether controlled to be a good one or not) will be an inductor of maybe 50nH.  ESD energy peaks in the 100MHz or below range, so the reactance of 10s of ohms in series with a ~300 ohm jolt will do roughly nothing.

Tim