Author Topic: How to intrepret the FT232HQ timing diagram?  (Read 778 times)

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Offline zaptaTopic starter

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How to intrepret the FT232HQ timing diagram?
« on: June 12, 2024, 04:10:26 am »
I am trying to interface an FTDI FT232HQ in asynchronous FIFO mode to an FPGA, datasheet here https://ftdichip.com/wp-content/uploads/2023/09/DS_FT232H.pdf#page=26 , and the relevant timing diagram is below.

The writing to the FIFO is done on the high-to-low transition of the WR# input. My question is, how long after the high-to-low transition of the WE# input it's safe to sample the TE# output to determine if the next byte can be written?  I would think it's max(t6)+max(t7) but max(t7) is not given.

 

Online PCB.Wiz

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Re: How to intrepret the FT232HQ timing diagram?
« Reply #1 on: June 12, 2024, 05:04:38 am »
My question is, how long after the high-to-low transition of the WE# input it's safe to sample the TE# output to determine if the next byte can be written? 
I would think it's max(t6)+max(t7) but max(t7) is not given.

My reading is you can sample for a low from T6, which is max 14ns, or you could wait for TXE high, which has a min of 49ns, then look for =\_
The lack of a MAX T7 might depend on the host reading the part so it could hit ms on a slow PC  ?
 

Online moffy

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Re: How to intrepret the FT232HQ timing diagram?
« Reply #2 on: June 12, 2024, 05:30:31 am »
Their TN_167 FIFO basics note states that for Asynchronous mode the maximum throughput is 8Mbyte/s, page 4 of: https://ftdichip.com/wp-content/uploads/2020/08/TN_167_FIFO_Basics.pdf
not sure if that helps, but it puts a limit on the maximum continuous write speed.
 

Offline zaptaTopic starter

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Re: How to intrepret the FT232HQ timing diagram?
« Reply #3 on: June 12, 2024, 05:36:58 am »
My reading is you can sample for a low from T6, which is max 14ns,...

I think this makes sense, after T6 it's high and then I can sample until TE# becomes low.
 

Offline zaptaTopic starter

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Re: How to intrepret the FT232HQ timing diagram?
« Reply #4 on: June 12, 2024, 05:41:33 am »
Their TN_167 FIFO basics note states that for Asynchronous mode the maximum throughput is 8Mbyte/s, page 4 of: https://ftdichip.com/wp-content/uploads/2020/08/TN_167_FIFO_Basics.pdf
not sure if that helps, but it puts a limit on the maximum continuous write speed.

That's a useful app note. I will read it. Thanks.

In my case I may need to spend also two cycles on FPGA input metastability protection so may be even slower but 4MB/s should be sufficient for my use case. Currently I do about 1.5MB/s blindly, ignoring the TE# signal and don't seem to loose bytes.
 


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