Memory - die pictures

[Noopy]

The orange surface is striking. Such an old design most likely did not use copper in the metal layer. Perhaps the color is due to the passivation.

This seems to be the case, because unpassivated areas of bonding parts are white. You may also see white elsewhere if you scratch the passivation layer on this kind of chips.

That could also be due to different metals in the bondpad area.
But I agree with you, probably it is due to the openings in the passivation layer.

[Noopy]

The 256kBit DRAM U61256 (https://www.richis-lab.de/RAM09.htm) was produced under the name UD61256 after the reunification of Germany. The Zentrum für Mikroelektronik Dresden was transformed into a limited liability company. The above component dates back to 1994. While only the selection type of the U61256 can represent access times of 80ns, the UD61256 with index 07 is specified with a maximum of 70ns. There is also an 08 variant with a guaranteed 80ns.




The dimensions of the die are 7,1mm x 3,6mm. This image of the die is also available in a higher resolution: https://www.richis-lab.de/images/RAM/15x02XL.jpg (38MB)




The designation UD61256 is shown on the right-hand side of the die. The number 4 probably stands for a fourth revision. The design dates back to 1991. The design was apparently revised again after the reunification of Germany.




In contrast to the U61256, the UD61256 has three additional bondpads. The location and connection suggest that there is a second data input and a second data output. The bondpad in the top right-hand corner cannot be assigned at first glance. It could be that a test mode has been integrated here, similar to the U61000 (https://www.richis-lab.de/RAM10.htm), which makes it possible to test parts of the memory simultaneously. This reduces the test time and therefore the manufacturing costs. The bondpad in the top right-hand corner could therefore be used to activate the test mode. The additional inputs and outputs could then be used to access two areas simultaneously, thus halving the test time. All three bondpads were contacted during production.




The die of the U61256 was still 9,6mm x 3,8mm. In the UD61256, the area has been reduced to 7,1mm x 3,6mm. The development of the area required for one DRAM memory cell is shown in the U61000 (https://www.richis-lab.de/RAM10.htm#area). The U61256 has therefore undergone an evolutionary stage in which the area was reduced from 77µm² to 50µm². The U61256 above is labeled as U61256-1. It is very likely that this is the initial layout.

The line selection in the right-hand area and the surrounding auxiliary circuits have been significantly reduced in size. The circuit has also been compressed. There are now significantly fewer free areas. The column evaluation has also been significantly reduced in size.




The memory area has also been optimized. It is still divided into four large blocks, which still contain 512 x 128 memory cells. The 16 reserve columns on the right edge have also been adopted from the U61256. However, the segments that make up the blocks have been enlarged in the UD61256. Instead of 64 columns, they now contain 96 columns.




The reserve columns are activated in the same way as the U61256. Two testpads are also integrated here, which enable fuses to be triggered in two blocks using the normal address interface. The fuses themselves are much harder to recognize here. They appear to have been slightly reduced in size. In addition, the silicone-like potting material with which the die was covered has accumulated in the space between the metal areas.


https://www.richis-lab.de/RAM12.htm

 

[Noopy]

As I already told you the 256kBit DRAM U61256 continued to be produced under the name UD61256 after the German reunification. The Zentrum für Mikroelektronik Dresden was transformed into a limited liability company. An updated datasheet exists for the UD61256. There was also the UD61259, but no information can be found on it. The component shown here was produced in 1992, slightly earlier than the UD61256 but already after reunification.




The dimensions of the die are 6,9mm x 3,6mm. This image is also available in a higher resolution: https://www.richis-lab.de/images/RAM/16x02XL.jpg (46MB)




The die was covered with a silicone-like protective layer. There are still residues. The designation U61256-3 is shown in the top right-hand corner of the die. This is obviously the third revision of the U61256. The copyright from 1989 shows that the design dates back to the time before the german reunification. As with the U2164 (https://www.richis-lab.de/RAM02.htm), an elephant is also depicted here.




While the die of revision 1 in the U61256 was still 9,6mm x 3,8mm, revision 3 in the UD61259 is only 6,9mm x 3,6mm. Revision 3 is very similar to revision 4 in the UD61256. Revision 4 appears slightly larger. However, this is only due to the fact that more silicon has been left at the edges outside the functional area. Revisions 3 and 4 are very similar, but you can clearly see that the design has been revised. Functionally, however, the two versions appear to be the same.

It remains unclear why the designation UD61259 was chosen for this variant. Perhaps there are too many memory cells which do not quite meet the specifications.


https://www.richis-lab.de/RAM13.htm

 

[Noopy]

The Intel D2164 is a 64kBit DRAM. The “20” variant offers a maximum access time of 200ns. A maximum access time of 150ns is specified for the “15” variant.




Application Note AP-131 from Intel contains a lot of information about the D2164. The 64kBit are divided into four areas with 128 x 128 memory cells. The cells are addressed with two sets of eight address bits. The first seven address bits activate one row in the upper and one row in the lower areas. The second seven address bits select one column each in the left and right blocks. In this way, the D2164 delivers the content of four memory cells in the first moment. The eighth address bit, which has also been latched twice, realizes the selection of one memory cell, which is then output. Data is written in the same way.




The dimensions of the die are 6,9mm x 3,7mm. The D2164 is based on the NMOS process HMOS-D III. The four-part division of the memory area is clearly visible.

This image is also available in a higher resolution: https://www.richis-lab.de/images/RAM/17x02XL.jpg (37MB)






The design dates back to 1981 and the A at the end of the designation 2164A could stand for a first revision.




The Application Note AP-131 claims that the D2164 was the first commercially produced RAM to incorporate spare cells. Each of the four areas contains two additional columns and two additional rows that can replace faulty memory cells and thus significantly increase the yield.




The reserve cells are assigned in the right-hand area of the die. Three testpads are integrated there for this purpose. This circuit is very similar to the spare cell configuration logic in the U2164 (https://www.richis-lab.de/RAM07.htm).




There are cut-outs above the fuses. No fuse was triggered on this D2164.




The application note describes the circuit for selecting the spare rows and spare columns in more detail. Each fuse is located in a so-called “programming element”, which has two transistors at the output. When the fuse is intact, the lower transistor is active. If the fuse is cut, the upper transistor becomes active. Vg and Vdp must be supplied via the testpads. The third testpad is not described in detail in the application note. On the die you can see that the current that triggers the fuse can flow through it. Intel has not disclosed how the individual fuses are selected. According to the circuit diagram, addressing is done with four lines. On the die you can see that the normal address lines are used to select the fuses. At least it seems like the normal adress lines control these programming elements.




The image above shows how spare rows are integrated into the address area. First you have to trigger the “Spare Row Enable” fuse. The associated spare row then becomes active at a row address. The configuration of the fuses determines which address is assigned to the spare row. For this purpose, each programmable element forwards either its address bit or the inverted address bit.

This explains the number of fuses. There are 32 fuses in the left-hand area and 36 in the right-hand area. If required, 4 fuses activate the two spare rows and the two spare columns. Four times 8 fuses can then be used to assign an address to each of the spare rows and spare columns.




Parallel to the circuit described, a logic ensures that the normal line selection remains inactive as long as the spare line is active.


https://www.richis-lab.de/RAM14.htm

 

[Noopy]

The Mikroelektronika Botevgrad CM8001 (SM8001) is an SRAM with a memory depth of 256 bits. It corresponds to the Intel 1101A. The 1101 was the second SRAM sold commercially by Intel. Intel supplied an improved version with the 1101A. Like the 1101 and the 1101A, the SM8001 is based on PMOS transistors and therefore requires a +5V potential and a -9V potential supply. The 1101 still had to be supplied with 5V, -7V and -10V. The 1101A had been optimized to such an extent that it could work with 5V and -9V. The access time of the SM8001 is specified with a maximum of 1,5µs. By selection it was possible to stay below 1µs. The marking shows that the component was manufactured in 1977.




The die of the SM8001 has been placed far off-center in the package.




The dimensions of the die are 3,1mm x 3,3mm.

This image is also available in a higher resolution: https://www.richis-lab.de/images/RAM/18x03XL.jpg (14MB)




800161 could be an internal designation.




In the center of each edge is a structure that shows how well the masks were aligned during production.




There are several test structures on the edges of the die. A resistor with a tap is integrated here.




These structures could be used to determine the leakage currents between the lines in the substrate. They could also be used to measure the parasitic capacitance.




The SM8001 is still based on a metal gate process in which the metal layer represents the gate electrodes of the MOS transistors. Where the metal layer is supposed to act as a gate electrode, there is a window with a gate oxide, a very thin silicon oxide layer in the thick, so-called field oxide. Intel has already manufactured the 1101 and the 1101A using a more modern silicon gate process. The polysilicon gate electrodes make it possible to produce more precise geometries.

The source and drain areas of the transistor integrated here are difficult to recognize. In other areas, the structures are more clearly visible. On the right, a resistor leads to a fourth testpad. The contact between the resistor and the drain/source area appears to occur without a special contact window.




Another test structure can be used to measure a parasitic MOSFET. This is a metal line that covers an insulation area between two lines in the substrate. Due to the thick field oxide, the charge of the metal line has a significantly lower influence on the underlying structures.




The functionality of the SM8001 is very clear. The address lines A0 to A3 are buffered, decoded (red) and finally activate one of 16 columns in two memory areas (yellow). The memory is divided into two blocks, each with 16x8 memory cells. The address lines A4 to A7 are also decoded (blue) and then select one memory row (green). Two lines run in the line selection area, which either transmit a differential signal to the respective memory cell or forward the state of the memory cell to the circuit in the upper left area.

The input buffer (pink) and the output driver (purple) are located in the upper left area. Both circuits are connected to the chip select and the R/W input. Like the 1101, the SM8001 also offers a complementary output to the data output. The two large push-pull output stages are clearly visible. In addition to the positive supply potential Vcc and the negative supply potential Vdd, the memory also has a Vd contact. Vd must also be connected to -9V and supplies the input and output circuits, while Vdd supplies the memory area itself.




The regular structure of the memory area is clearly recognizable. It consists of blocks, each containing two memory cells.




There is a Vcc line below each memory cell. The Vdd potential is located at the top and bottom. These Vdd lines are also used by the memory cells at the top and bottom. The word lines, which activate the corresponding column of the memory, run to the right and left of the two memory cells in the substrate. The two horizontal bit lines transmit the status of the selected memory cell.




The SM8001 is based on 4T memory cells containing four PMOS transistors and two resistors.


https://www.richis-lab.de/RAM15.htm

 

[Noopy]

800161 could be an internal designation.

That´s probably "8001 Б1". And Б1 (cyrillic B1) shows the design revision.