Electronics > Projects, Designs, and Technical Stuff
Understanding LTspice "SolarCell" model
Peabody:
Trying to make my way up the learning curve, I found this LTspice model for a solar-powered battery charger:
http://www.linear.com/docs/40736
What I'm interested in is the input source from the U2 diode(?) on the left, and what appears to be its definition just below:
--- Code: ---SYMATTR InstName U2
SYMATTR Value PhotoCell
SYMATTR Prefix X
.subckt PhotoCell B A
C1 A B 1n
V1 N001 B PWL(0 0 3u 17.7)
D1 N001 A S2
R1 A N001 75
.model S2 D(Ron=.1 Ilimit=1.2 epsilon=.5)
.ends
--- End code ---
Could someone explain what's going on here? What is a .model S2 D? Is there a way to see this subcircuit - how C1, V1, D1 and R1 are connected?
Ian.M:
Plot it out from the netlist! Its a diode of type 'S2' in parallel with a 75R resistor, with a PWL voltage source in series with the pair. The model for 'S2' is given, but to understand it, you need to know that its using a simplified curve-fit model, not modelling the semiconductor physics involved. See: https://www.analog.com/en/technical-articles/ltspice-simple-idealized-diode.html
IMHO it should have either been parametrized, with solar irradiance as a parameter, or given a third terminal with solar irradiance as a control voltage . . .
Peabody:
Thanks very much for the reponse, but I don't know what any of that means. How would I plot it out from the netlist? What netlist? And where is the model for S2 "given"?
Well, I don't want to waste your time on this. If you know of a video that covers all of this, it might be easier to just provide a link to that.
Ian.M:
Sorry, I don't have a video link for you as I learnt it the easy(ish) way of RTFM, research and experimenting, rather than the hard way of trying to replicate the steps in a Youtube video on a 'Monkey see, Monkey do' basis.
The netlist for the PhotoCell model is given between the .subckt line and the .ends line. Its name and pins in order are given on the .subckt line.
To reverse engineer it back to a schematic, start with a blank schematic in a new folder. This time, lets name the folder "revengnetlist" (no quotes).
Step1: add net labels of port type Bi-Direct for each pin named on the .subckt line (unless the pin is always an input or output, in which case you use those port types). All 'boxed' net labels become a subcircuit pin.
Step2: add 'C1 A B 1n' by placing a 1n capacitor, and connecting it to A and B. Check the new netlist (Menu: View: SPICE Netlist). If C1's connections are in the wrong order, flip it.
Step3: add 'V1 N001 B PWL(0 0 3u 17.7)' by placing a Voltage source V1 with value PWL(0 0 3u 17.7). Connect one pin to B and net label its other pin N001. Check the new netlist (Menu: View: SPICE Netlist). If V1's connections are in the wrong order, flip it.
Step4,5: add remaining components as above, checking the new netlist after each.
Step6: Add the model line for the diode type S2 by placing a SPICE directive:
--- Code: ---.model S2 D(Ron=.1 Ilimit=1.2 epsilon=.5)
--- End code ---
and again check the new netlist matches the subcircuit model you are reverse engineering.
The result should look something like this:
and its netlist should be:
--- Code: ---* C:\users\<Your_User_Name>\documents\<Your_LTspice_Work_Folder>\revengnetlist\photocell.asc
C1 A B 1n
V1 N001 B PWL(0 0 3u 17.7)
D1 N001 A S2
R1 A N001 75
.model D D
.lib C:\Users\<Your_User_Name>\Documents\LTspiceXVII\lib\cmp\standard.dio
.model S2 D(Ron=.1 Ilimit=1.2 epsilon=.5)
.backanno
.end
--- End code ---
Stuff in <> will be specific to your Windows user name. The lines .model D D, .lib C:\...\lib\cmp\standard.dio and .backanno are auto-supplied by LTspice with standard control panel options. Ignore them, they'll vanish when you use the reverse engineered model as a Hierarchical sub-schematic, and the .subckt and .ends lines will be auto-added.
All the steps so far are in the attached zip file. Note that if the subcircuit is complex, you'll need to spend a fair bit of time rearranging the layout to make sense, repeatedly checking that you haven't messed up the new netlist as you do so. For components with more than two pins, flipping them will not fix an incorrect pin order. Its easiest to start by labelling all the pins with a temporary distinct net label as soon as you've placed it, before you make any other connections to the component, then check the new netlist to get the pin order then hook them up one pin at a time, checking the new netlist, and removing the extra temporary net labels as you do so. Also note that any comments will always appear at the end of the new netlist, not in the order you placed them, and the components and directives.
Next we need to make it usable as a Hierarchical sub-schematic (See help LTspice XVII: Schematic Capture: Hierarchy). Save it as PhotoCell.asc and create a symbol of the same name for it. (Hint - Menu: Hierarchy: Open this Sheet's Symbol - will autogenerate a Hierarchical symbol with as many pins as labels with a Port-Type other than 'None' in your schematic, already pre-labelled and in correct netlist order.) Use your artistic talents to re-draw it as required. Check the pin table (Menu: View: Pin Table) is correct, and save it. (I cheated and stole the LED symbol then munged it to suit.)
Finally create a test jig schematic in the same folder and place an instance of 'PhotoCell' on it by selecting the current folder ion the 'Top Directory' dropdown at the top of the dialog then selecting it. Wire it up and run it!
N.B. The symbol attributes Prefix, SpiceModel and ModelFile *MUST* remain blank, the symbol type must be Block and the .asy name must exactly match the .asc name of the Hierarchical sub-schematic, and both + the main schematic must be all in the same folder for LTspice to recognize it as a Hierarchical sub-schematic when you run the main schematic sim.
Jay_Diddy_B:
Hi,
In this example the solar cell is modeled as current-limited voltage source.
The diode D1 in the model is not a normal diode. It is a current limiter. It limits the maximum current to 1.2A.
Jay_Diddy_B
Navigation
[0] Message Index
[#] Next page
Go to full version