Understanding LTspice "SolarCell" model

[Peabody]

Trying to make my way up the learning curve, I found this LTspice model for a solar-powered battery charger:

http://www.linear.com/docs/40736

What I'm interested in is the input source from the U2 diode(?) on the left, and what appears to be its definition just below:

Code: [Select]

SYMATTR InstName U2
SYMATTR Value PhotoCell
SYMATTR Prefix X

.subckt PhotoCell B A
C1 A B 1n
V1 N001 B  PWL(0 0 3u 17.7)
D1 N001 A S2
R1 A N001 75
.model S2 D(Ron=.1 Ilimit=1.2 epsilon=.5)
.ends

Could someone explain what's going on here?  What is a .model S2 D?  Is there a way to see this subcircuit - how C1, V1, D1 and R1 are connected?

[Ian.M]

Plot it out from the netlist!  Its a diode of type 'S2' in parallel with a 75R resistor, with a PWL voltage source in series with the pair. The model for 'S2' is given, but to understand it, you need to know that its using a simplified curve-fit model, not modelling the semiconductor physics involved.  See: https://www.analog.com/en/technical-articles/ltspice-simple-idealized-diode.html

IMHO it should have either been parametrized, with solar irradiance as a parameter, or given a third terminal with solar irradiance as a control voltage . .  .

[Peabody]

Thanks very much for the reponse, but I don't know what any of that means. How would I plot it out from the netlist?  What netlist?  And where is the model for S2 "given"?

Well, I don't want to waste your time on this.  If you know of a video  that covers all of this, it might be easier to just provide a link to that.

[Ian.M]

Sorry, I don't have a video link for you as I learnt it the easy(ish) way of RTFM, research and experimenting, rather than the hard way of trying to replicate the steps in a Youtube video on a 'Monkey see, Monkey do' basis.

The netlist for the PhotoCell model is given between the .subckt line and the .ends line.  Its name and pins in order are given on the .subckt line.

To reverse engineer it back to a schematic, start with a blank schematic in a new folder.  This time, lets name the folder "revengnetlist" (no quotes).

Step1: add net labels of port type Bi-Direct for each pin named on the .subckt line (unless the pin is always an input or output, in which case you use those port types).  All 'boxed' net labels become a subcircuit pin.

Step2: add 'C1 A B 1n' by placing a 1n capacitor, and connecting it to A and B.  Check the new netlist (Menu: View: SPICE Netlist).  If C1's connections are in the wrong order, flip it.

Step3: add 'V1 N001 B  PWL(0 0 3u 17.7)' by placing a Voltage source V1 with value PWL(0 0 3u 17.7).  Connect one pin to B and net label its other pin N001.    Check the new netlist (Menu: View: SPICE Netlist).  If V1's connections are in the wrong order, flip it.

Step4,5: add remaining components as above, checking the new netlist after each.
 
Step6: Add the model line for the diode type S2 by placing a SPICE directive:

Code: [Select]

.model S2 D(Ron=.1 Ilimit=1.2 epsilon=.5)and again check the new netlist matches the subcircuit model you are reverse engineering.

The result should look something like this:



and its netlist should be:

Code: [Select]

* C:\users\<Your_User_Name>\documents\<Your_LTspice_Work_Folder>\revengnetlist\photocell.asc
C1 A B 1n
V1 N001 B PWL(0 0 3u 17.7)
D1 N001 A S2
R1 A N001 75
.model D D
.lib C:\Users\<Your_User_Name>\Documents\LTspiceXVII\lib\cmp\standard.dio
.model S2 D(Ron=.1 Ilimit=1.2 epsilon=.5)
.backanno
.end
Stuff in <> will be specific to your Windows user name. The lines .model D D, .lib C:\...\lib\cmp\standard.dio and .backanno are auto-supplied by LTspice with standard control panel options.  Ignore them, they'll vanish when you use the reverse engineered model as a Hierarchical sub-schematic, and the .subckt and .ends lines will be auto-added.

All the steps so far are in the attached zip file.  Note that if the subcircuit is complex, you'll need to spend a fair bit of time rearranging the layout to make sense, repeatedly checking that you haven't messed up the new netlist as you do so. For components with more than two pins, flipping them will not fix an incorrect pin order.  Its easiest to start by labelling all the pins with a temporary distinct net label as soon as you've placed it, before you make any other connections to the component, then check the new netlist to get the pin order then hook them up one pin at a time, checking the new netlist, and removing the extra  temporary net labels as you do so.  Also note that any comments will always appear at the end of the new netlist, not in the order you placed them, and the components and directives.

Next we need to make it usable as a Hierarchical sub-schematic (See help LTspice XVII: Schematic Capture: Hierarchy).  Save it as PhotoCell.asc and create a symbol of the same name for it. (Hint - Menu: Hierarchy: Open this Sheet's Symbol - will autogenerate a Hierarchical symbol with as many pins as labels with a Port-Type other than 'None' in your schematic, already pre-labelled and in correct netlist order.)  Use your artistic talents to re-draw it  as required. Check the pin table (Menu: View: Pin Table) is correct, and save it.   (I cheated and stole the LED symbol then munged it to suit.) 

Finally create a test jig schematic in the same folder and place an instance of 'PhotoCell' on it by selecting the current folder ion the 'Top Directory' dropdown at the top of the dialog then selecting it.  Wire it up and run it!

N.B. The symbol attributes Prefix, SpiceModel and ModelFile *MUST* remain  blank, the symbol type must be Block and the .asy name must exactly match the .asc name of the Hierarchical sub-schematic, and both + the main schematic must be all in the same folder for LTspice to recognize it as a Hierarchical sub-schematic when you run the main schematic sim.

[Jay_Diddy_B]

Hi,

In this example the solar cell is modeled as current-limited voltage source.

The diode D1 in the model is not a normal diode. It is a current limiter. It limits the maximum current to 1.2A.

Jay_Diddy_B

[Ian.M]

Good point, Jay. 

The page I linked (Reply #1 above) at Analog.com does touch on current limiting: "...  The forward conduction and reverse breakdown can further be specified with current limit parameters Ilimit and revIlimit. ..." but it isn't obvious.

To see the characteristic, replace the test jig in RevEngNetlist with this one, and plot V(vcell) and Ix(u2:B), which is the current at the cathode of U2, the photocell.

IMHO Its not a very good solar cell model . . .

[Jay_Diddy_B]

Hi Ian.m and the group,

You demonstrated the 'joy' of disappearing user defined models in LTspice when sharing circuits. The solar cell model is missing in your attachment.

If I draw the solar cell model, so it is included in the model:




I have put the model in a circuit to show the maximum power point.

Widely Used Model

Here is a widely used model. I have added a sunshine input. This shows how the output changes with differently levels of sunshine, insolation.




Adjust N. in the Dsolar model, and Rs to match the panel being used.

I have attached the models.

Regards,
Jay_Diddy_B

 solar cell sim jdb.asc (1.34 kB - downloaded 210 times.)

 PhotoCell Test2.asc (1.32 kB - downloaded 169 times.)

[Ian.M]

Yes, my "PhotoCell Test2.asc" is not a complete standalone sim - I *thought* I'd made it clear that it needed the files from RevEngNetlist.zip (specifically the hierarchical sub-schematic PhotoCell.asc and its symbol PhotoCell.asy), but if you thought otherwise, obviously not!

Thankyou for providing the standalone version with the hierarchy 'flattened' to a single schematic, and for going 'above and beyond' and posting a better solar panel model. 

[Peabody]

Thanks very much.  It will  take me some time to absorb this information.

But going back to the first circuit, does "S" or "S2" refer to a component type, or is it just a name the designer picked?  Could it be "Q4" instead?

Here's the solar panel I've used so far.  As I understand it, it models a single cell, then multiplies that by the number of cells in series to produce the open circuit voltage.  But I didn't see any way to address the parallel cells other than to fudge the numbers until Isc came out right, which I did.  Is this not a good model to use?

[Ian.M]

Lets consider the line:

Code: [Select]

.model S2 D(Ron=.1 Ilimit=1.2 epsilon=.5)That's a SPICE model statement that defines S2 as a somewhat peculiar diode (as Jay_Diddy_B explained earlier).  Obviously the part 'number' S2 cant conflict with any other .model statement, and LTspice defaults to auto-including the standard libraries for diodes, BJTs, JFETs and MOSFETs, which all use .model statements, so you should avoid any part 'number' in those libraries. (I don't know if the different types of .model are in separate namespaces, so I wouldn't risk reusing e.g. a JFET part no. for a diode.)  Otherwise its free choice of part 'number' - you can even use pure numerics which can be useful if you want to .step a sim through a selection of different semiconductors.

Paralleling individual solar cells is equivalent to simply increasing the cell area, so your approach of fiddling with the parameters to get the correct Isc is acceptable if somewhat awkward.  However F1 in your model is a current dependent current source that feeds back the load current into the 'guts' of the model and if you change its value from 1 to 1/{m}, you can then set parameter m to the number of parallel cells (or strings) to scale the feedback without having to fiddle with the parameters of an individual cell.

[Peabody]

Thanks very much.  That method of incorporating the parallel structure to get the current right makes a lot more sense than what I was doing.

There are a number of LTspice tutorials on Youtube, but most are seven years old, which I assume means they are based on version 4.  Would you expect them to still be relevant?  What I downloaded from AD was version 17. 

[Ian.M]

LTspice XVII is pretty much backwards compatible with IV.  There are a few UI changes e.g. custom dialogs for many SPICE dot commands, but you can generally ignore them and edit the raw command line if you must.  Various menus have undergone considerable changes, the most notable being the context menu, and the supplied device library has grown considerably, but if you dig around a bit you should be able to find everything IV had.

One annoyance is that LTspice IV did not let you set the font size of component attributes, displaying them all as size '1.5'.  XVII lets you set the size (nice) but unfortunately when you open an .asc file created in IV, it tends to set them to size '0.625', which is generally too small to read (although it defaults to '1.5' when you place a new component).

If you follow any LTspice IV tutorial with more thought and consideration than 'monkey see, monkey do' it should still work OK and be relevant under XVII, though there may be an easier XVII specific way of achieving the same result.   Links to legacy resources on the WWW may well be broken so expect to have to stretch your Google-fu and/or use the Internet Archive to locate any missing files the tutorial author chose not to host.

Its also highly compatible with Berkeley SPICE 3 at the netlist and model syntax level, so if you are creating or modifying models or subcircuits that fit the measured (or nominal) parameters of real-life components, academic resources and tutorials from as far back as the 1990s are still relevant.  Just make sure any models you import wholesale that aren't LTspice specific, are in 'vanilla' Berkley SPICE 3 syntax, as some 3rd party SPICEs have proprietary extended netlist syntax that's incompatible.  Symbols, GUI schematics and encrypted models for other SPICE programs are *NOT* importable by LTspice.

[Jay_Diddy_B]

Hi Peabody and the group,

The SM531K08L datasheet gives:




This is the performance, per unit area (cm²) of a single cell.




From this table we can deduce that there are 8 cells in series in the SM531K08L




From the physical dimensions the area is 45 cm². From this we can obtain the maximum output power.

LTspice model for a SM531K08L



A sunshine input of 1V corresponds to an insolation of 1000W/m²

Running the simulation reveals:




This matches the datasheet very closely.

V_mpp = 4.53 versus 4.46V (datasheet)

P_mpp = 906mW versus 913mW (datasheet)

Arrays of multiple SM531K08L


These can be modelled like this:




This is a series parallel, 3 x 2, array of SM531K08L panels.

Regards,
Jay_Diddy_B

 solar cell sim jdb.asc (1.34 kB - downloaded 136 times.) multiple solar cells sim jdb.asc (1.75 kB - downloaded 133 times.)

[floobydust]

That's nice work, thanks I will give it a try. How did you come up with values for Rp and Rs?
I have some garden light solar cells I wanted to model (as soon as it becomes sunny outside) because at that low power level, MPP is not practical and the dilemna is what voltage and current works well in partial sun. I reverse-engineered some Ikea solar lights and all use a single 1.2V NiMH cell, but 4 or 8 cells feeding the IC.
Bolting on a solar panel to a boost/buck converter, I find the input capacitor is critical to achieve the high peak current, yet this is not on the datasheets LT3652 included with its little 10uF part. So OP putting together the two sims would be worth it.

[Zero999]

Solar cells have a negative temperate co-efficient. It might be useful to add another temperature input.

[Jay_Diddy_B]

Hi,
To expand the model to include temperature.

Datasheet




The datasheet shows how the short circuit current increases with temperature and the open circuit voltage decreases.

Modified Model




A parameter, Tc, the temperature of the solar cell has been added to model.




This shows that the short circuit current increases at rate of 98.74uA per degree C versus the datasheet 98.5uA / C.

Open Circuit Voltage versus Temperature




And the result:




The model is giving -13.6mV / C versus the datasheet -13.9mV/C

Maximum Power Point versus Temperature






I have attached the models used.

Regards,
Jay_Diddy_B
 multiple solar cells sim with temp jdb ISC test.asc (2.02 kB - downloaded 129 times.) multiple solar cells sim with temp jdb voC test.asc (1.88 kB - downloaded 106 times.) multiple solar cells sim with temp jdb mpp test.asc (2.01 kB - downloaded 156 times.)