Electronics > Projects, Designs, and Technical Stuff
Unexpected amount of heat
Siwastaja:
--- Quote from: OM222O on May 12, 2019, 06:07:08 pm ---there are a ton of vias stiching ground planes under screws and on the edges of the board that are in close proximity of the device.
--- End quote ---
These help a bit, tying the ground planes together thermally, but the collector pad coupling to this plane will be poor if you have (assumably) 1.6mm of FR4 inbetween. If you must have ground potential on the bottom copper (your front panel), then the best thing you could do to improve thermals is to use a 4-layer board, with the stackup that has minimized distance between the top layer and the adjacent mid layer. 100um separation is 16x improvement compared to the standard 2-layer stackup! Then, this mid layer needs to transfer heat sideways a bit, to reach all the ground vias, use a lot of them. Use 2oz copper to further improve the thermals, but again, this tends to increase PCB cost further. Much better than what you have now, but I understand that a 4-layer PCB would add cost. I guess you could get down to around 20 degC/W with this. Maybe if you combined this approach with an SMD heatsink of about 10 degC/W, the combined thermal resistance of around 7 degC/W might be acceptable for the 9W dissipation, just maybe?
But I don't know whether such optimization for the peak load dissipation makes much sense - as you have identified, your dissipation is pulsed, and your duty cycle is low, with pulse length of only 2s, and period of 7s, peak power of 9W, and average power of 2.6W. Now, while the D2PAK with a standard footprint isn't capable of handling this 2.6W average dissipation, it should be achievable with enlarged copper area, and coupling through FR4 to your stitched ground planes. The excercise left for you, indeed, is to guarantee staying within this duty cycle, and pulse length, and hence, average power, without assuming anything about how the user behaves. Again, a simple thermistor logically preventing the operation (preventing base drive, for example) in case of overtemp might be the simplest, as it wouldn't need to handle power. Depending on your actual circuit, of course.
IanB:
--- Quote from: OM222O on May 12, 2019, 01:59:34 pm ---The Collector is connected to +12V and the emitter is kept at 1V with the shunt resistor being 1\$\Omega\$. I calculated the temperature rise to be 11 degrees which I knew is extremely optimistic, but it was based on the data sheet values.
Thermal resistance is given to be 1C/W and the power dissipation is (12-1)*(1/1) = 11 watt. 11 volts at 1A.
--- End quote ---
To give you some kind of reference to guide your thinking, consider a small incandescent lamp, e.g. 6 V, 1 A, 6 W, or 12 V, 1 A, 12 W. Consider that the filament of such a bulb glows white hot, and the glass envelope of the bulb will become too hot to touch after only a short time running (you will probably burn your fingers on the 12 V lamp).
Now consider the small piece of silicon inside the transistor, of roughly the same area/volume as the filament of the lamp. Imagine this also glowing white hot under a similar level of power dissipation.
This may give you some grounding in the (considerable) amount of heat sinking you need for the package if it is to have any hope of surviving.
Gyro:
A 6W soldering iron analogy would be more appropriate and understandable than a filament lamp.
IanB:
Whatever gives an appreciation of what 6 - 12 W of heat generation means should be helpful. The thread title about an "unexpected" amount of heat is slightly strange. Anything that generates that amount of heat in a small space is going to get very, very hot. Hot enough to burn your fingers.
OM222O:
--- Quote from: Siwastaja on May 12, 2019, 06:51:56 pm ---
--- Quote from: OM222O on May 12, 2019, 06:07:08 pm ---there are a ton of vias stiching ground planes under screws and on the edges of the board that are in close proximity of the device.
--- End quote ---
These help a bit, tying the ground planes together thermally, but the collector pad coupling to this plane will be poor if you have (assumably) 1.6mm of FR4 inbetween. If you must have ground potential on the bottom copper (your front panel), then the best thing you could do to improve thermals is to use a 4-layer board, with the stackup that has minimized distance between the top layer and the adjacent mid layer. 100um separation is 16x improvement compared to the standard 2-layer stackup! Then, this mid layer needs to transfer heat sideways a bit, to reach all the ground vias, use a lot of them. Use 2oz copper to further improve the thermals, but again, this tends to increase PCB cost further. Much better than what you have now, but I understand that a 4-layer PCB would add cost. I guess you could get down to around 20 degC/W with this. Maybe if you combined this approach with an SMD heatsink of about 10 degC/W, the combined thermal resistance of around 7 degC/W might be acceptable for the 9W dissipation, just maybe?
But I don't know whether such optimization for the peak load dissipation makes much sense - as you have identified, your dissipation is pulsed, and your duty cycle is low, with pulse length of only 2s, and period of 7s, peak power of 9W, and average power of 2.6W. Now, while the D2PAK with a standard footprint isn't capable of handling this 2.6W average dissipation, it should be achievable with enlarged copper area, and coupling through FR4 to your stitched ground planes. The excercise left for you, indeed, is to guarantee staying within this duty cycle, and pulse length, and hence, average power, without assuming anything about how the user behaves. Again, a simple thermistor logically preventing the operation (preventing base drive, for example) in case of overtemp might be the simplest, as it wouldn't need to handle power. Depending on your actual circuit, of course.
--- End quote ---
I will order some PTCs with a few different values and carry out some tests. guaranteeing the low on time can easily be achieved in software and it's not an issue. also the plane as about 10 mil gap to the sides, it doesn't have to pass through the entire 1.6mm of FR4 (just a few mills to jump to the ground plane ... I'm not sure how to calculate that). I just wonder if the thermal mass is large enough to prevent the transistor from breaking again (in the 2second on time) like the previous one did, as it will short out the op amp too (about 5$ damage replacing both of them) unless I include some schottky diodes from op amp output to +5V rail and rely on the 1k base resistor to limit the current ??? generally speaking it won't be under that amount of load for much longer than 2 second anyways since measurements aren't repeated back to back, again I'm just assuming a worst case scenario here since it happened with the other transistor ... it was just too much for the poor thing to handle. I'm not sure if the die will reach the specified 150C within 2 seconds or not and there isn't a simulation tool which I can use to find out :palm:
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