Electronics > Projects, Designs, and Technical Stuff
Upgrading eMMC and RAM of Chromebook possible?
FrankE:
I've a Chromebook which came with 32GB eMMC and 4GB soldered-in SMD RAM.
I've flashed it with a full Mr Chromebox BIOS and installed GalliumOS on it.
Acer C730 Gnawty aka Chromebook 11. Bay Trail
It's currently being used as my main computer while waiting for a replacement PSU for my desktop.. It's usable as long as I use hook it up to a proper monitor and use a wirless keyboard and mouse but it can't do anything remotely demanding
If I can source an eMMC with the same pinout and RAM with the same pinout would it just be a straight swap?
IIRC when I briefly looked into this before the devices are by Hynix.
The desoldsering and soldering isn't the issue - I've no idea how the memory is addressed on this thing.
sudo lshw -c memory
[sudo] password for **
*-firmware
description: BIOS
vendor: coreboot
physical id: 0
version: MrChromebox-4.9
date: 01/04/2019
size: 1MiB
capacity: 8128KiB
capabilities: pci pcmcia upgrade bootselect acpi
*-memory
description: System memory
physical id: 1
size: 3864MiB
There are all sorts of loops for the audio to work.
df -H
Filesystem Size Used Avail Use% Mounted on
udev 2.1G 0 2.1G 0% /dev
tmpfs 406M 1.6M 404M 1% /run
/dev/mapper/galliumos--vg-root 30G 6.9G 22G 25% /
tmpfs 2.1G 302M 1.8G 15% /dev/shm
tmpfs 5.3M 4.1k 5.3M 1% /run/lock
tmpfs 2.1G 0 2.1G 0% /sys/fs/cgroup
/dev/loop0 51M 51M 0 100% /snap/gtk-common-themes/1474
/dev/loop1 78M 78M 0 100% /snap/wine-platform-3-stable/6
/dev/loop3 29M 29M 0 100% /snap/snapd/6953
/dev/loop4 58M 58M 0 100% /snap/core18/1705
/dev/loop2 26M 26M 0 100% /snap/snapd/6434
/dev/loop5 4.2M 4.2M 0 100% /snap/notepad-plus-plus/227
/dev/loop6 238M 238M 0 100% /snap/wine-platform-runtime/104
/dev/mmcblk0p2 739M 51M 635M 8% /boot
/dev/mmcblk0p1 536M 9.8M 527M 2% /boot/efi
tmpfs 406M 8.2k 406M 1% /run/user/1000
amyk:
For RAM, it should work unless the BIOS was hardcoded to a specific size, and/or the CPU physically doesn't have the address lines to support the larger size.
For eMMC, it's a little more flexible but beware of features like password protection and such which tie the contents to another unique ID on the motherboard.
magic:
I don't think the Chromebooks use any security features of eMMC. They have a software security architecture which verifies if the code running on the machine does indeed come from Google and that's about it. Last time I looked they didn't even encrypt user data. And if they did, I expect that Google wouldn't trust eMMC vendors and would roll their own.
As for RAM, the magic word is "SPD" (serial presence detect). It's an I2C EEPROM with information about the memory, normally present on each DIMM. If this is present on the motherboard, you will need to reprogram it with information about new RAM. No rocket science, you take some numbers from the DRAM datasheet and encode them per the SPD spec. If it is not present, and I expect that this is the case, then the information must be stored in the boot ROM and you will need to write-unprotect the machine and modify it. RAM chips by themselves offer absolutely zero autodetection functionality.
It seems you have Linux on that thing, can you run i2cdetect -l for starters?
FrankE:
Yes I put a MrChromebook BIOS on it and Gallium OS
sudo apt-get install i2c-tools
i2cdetect -l
i2c-3 unknown i915 gmbus vga N/A
i2c-1 unknown Synopsys DesignWare I2C adapter N/A
i2c-8 unknown DPDDC-C N/A
i2c-6 unknown i915 gmbus dpb N/A
i2c-4 unknown i915 gmbus panel N/A
i2c-2 unknown i915 gmbus ssc N/A
i2c-0 unknown Synopsys DesignWare I2C adapter N/A
i2c-9 unknown DPDDC-B N/A
i2c-7 unknown i915 gmbus dpd N/A
i2c-5 unknown i915 gmbus dpc N/A
magic:
Hmm, not sure which of those (if any) would be the main SMBUS. But I will tell you what, I suspect the SPD data are embedded in the boot ROM anyway. See if you can find any EEPROM chip on the board or a leaked schematic of the laptop (those are surprisingly common, actually).
edit
Or look for the source code of ChromeOS boot firmware for your platform. It will probably contain the SPD or some placeholder for it or other indication that the thing should be present. Maybe you will find some discussion on mailing lists, bugs or places like that. Or maybe you will find a confirmation that they use a separate I2C chip on the board, but why would they bother?
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