USB JTAG Programmer - PCB Layout Advice

[charliex]

turned out well.

[jahonen]

David,

Nice to see your design turned out to be good after all. However, I have found out several times that don't pop the champagne until it all works

In case you still wondering about whether to do your next FPGA project you mentioned with 2 or 4 layers, maybe this will make it easier to decide. That is a Altera Cyclone II EP2C8, 144 pins and not even near of all the IO:s routed. As you can see, there are hefty number of VCC and GND pins (for a good reason, the IO drive capability is quite impressive). I'm using 0.8 mm diameter vias (with 0.4 mm hole) on the GND and VCC pins on the FPGA and still the damn thing feels like huge blob when placed next to the FPGA pins. The core voltage regulator is underside of the chip, along with the bypassing. I'm planning to use first-to-plane-and-then-to-pin-strategy for powering this thing, although it is not the best thing with only 4 layers, as the inner layers are quite far apart (about 1 millimeter).

Cyclone III is even more difficult beast since it requires three voltages (or even four if using DDR-interface) (unless you use 2.5 volt IO:s), one for the core (1.2 V), one for the PLL:s (2.5 V) and finally the IO-voltage (e.g. 3.3 V)

Regards,
Janne

[David]

David,

Nice to see your design turned out to be good after all. However, I have found out several times that don't pop the champagne until it all works

In case you still wondering about whether to do your next FPGA project you mentioned with 2 or 4 layers, maybe this will make it easier to decide. That is a Altera Cyclone II EP2C8, 144 pins and not even near of all the IO:s routed. As you can see, there are hefty number of VCC and GND pins (for a good reason, the IO drive capability is quite impressive). I'm using 0.8 mm diameter vias (with 0.4 mm hole) on the GND and VCC pins on the FPGA and still the damn thing feels like huge blob when placed next to the FPGA pins. The core voltage regulator is underside of the chip, along with the bypassing. I'm planning to use first-to-plane-and-then-to-pin-strategy for powering this thing, although it is not the best thing with only 4 layers, as the inner layers are quite far apart (about 1 millimeter).

Cyclone III is even more difficult beast since it requires three voltages (or even four if using DDR-interface) (unless you use 2.5 volt IO:s), one for the core (1.2 V), one for the PLL:s (2.5 V) and finally the IO-voltage (e.g. 3.3 V)

Regards,
Janne

Ah yes I am certainly not celebrating yet!

Regarding my next project, I feel a 4 layer board is now the way to go. My idea to handle the VCC pins is to put vias directly behind the vcc pins (I.e. under the FPGA itself) and then straight down to the power plane. I think I might have to route tracks of different voltages through the power plane (2.5V, 1.2V) as well to the appropriate pins as I plan on having it filled with 3.3V (I'm using 3.3V for all I/O).

Dave

[David]

So the nightmare of my latest project has just started. Attached is my first go at a very rough layout for my board (Just major component placement). The problem I have is that the RAM/ROM and all those 74HC245 latches share the same address/data buses (the latches just use the data). The data and address buses are 16-bits wide but the latches only use 8-bits of the data each. For this reason ive tried to keep them all as close as possible. Its a right pain that I can't get the RAM/ROM in the same packages too!



Dave

[jahonen]

It seems that you are integrating the USB-blaster on the board, why not just use separate one, makes the layout somewhat simpler? Also, '245 is a bidirectional buffer, not a latch. Did you mean '373? Really not enough IO's for separate address and data buses?

I used just array of small 0.3 mm diameter vias on the thermal pad, but that requires hot air soldering.

IMO, it makes easier to place the parts when all the power/gnd unroutes/airwires/ratsnest are hidden and just pins colored differently. Especially so with multilayer boards, where VCC and GND are available anywhere on the board. I'm not sure if Eagle supports that.

Regards,
Janne

[David]

Hey everyone,
I need some opinions on my routing style. Attached is a picture that shows how I am using filter caps to the ground plane (By placing a via at the end of the caps that goes to the ground plane) Is this a good way of de-coupling? Should I connect ground points of the same IC in the signal layer and then use only a few vias to the groundplane instead?

Thanks,
Dave

[jahonen]

I think that your routing style is quite similar to that I use. Connecting the capacitors directly to the plane is ok. For the FPGA, connect the ground pins directly to the plane and don't share the vias, use own via for each ground pin. Also, connect VCC plane directly to the capacitor (like ground), not from the inside end of the FPGA package, although that looks tempting from space point of view

What you'll want, is a low inductance connection between the capacitor and the FPGA. This can be accomplished by routing the current and its associated ground current on layers with close proximity. With 4-layer buildups, 1-2 and 3-4 are very close (something like 0.2 mm apart).

Regards,
Janne

[David]

Why is it a bad idea to place vias to Vcc behind the pins (under the IC) ? I'm really starting to think this board isn't routable now! Its a nightmare! 

[jahonen]

See pages 100 and 108 of this nice PDF one of my colleagues found. Quite recently, I ended up connecting the pins and capacitors both directly to the planes. And to reduce the congestion of the routing area, I did put the core VCC decoupling capacitors to the bottom side of the PCB, just under the FPGA. Here is the screenshot from the layout, but unfortunately not very detailed. However, this PDF shows the layout in more detail.

Don't give up just yet, that requires just a little thought. Also, reduce the component size (decoupling caps) if at all possible. That might make it easier.

Regards,
Janne

[David]

I thought I would post an update of the board so far, although its still a long way off. I kept up my persistence and what first appeared to be impossible has worked out fairly well IMO. While I'm here I'd just like to ask peoples opinions on using wider tracks mixed with smaller ones...What I mean by this is that I've used 0.016" tracks from most of my I/O (ie the switches, leds etc) to in-line resistors and then 0.01" tracks to the FPGA so that I can fit them in. I am now thinking it looks neater to use 0.01" all round? (Obviously not for high current etc..)

Dave



(Update) Routing Example:

[TheDirty]

10mil tracks are perfectly acceptable for these small signal lines.  Generally I don't care about what looks best with track size, though and usually go with the largest trace that I can place without going overboard.  The layout is looking really nice.  Is there a reason you wont put components on the bottom of the board?  Those decoupling caps would work out well on the bottom.

My own quirk is just trying to shove in everything as tight as possible.

[David]

Thanks for the comments. Are you reffering to the big white space on the left-hand side? If so, that's for an LCD display that will plug in.

[TheDirty]

No, sorry, that wasn't a comment on your board.  I was just commenting of preferences when it comes to layout.  You like to have balanced looking track sizes and I'll do everything I can to jam components as close together with the smallest board size possible.  I think it's like those people that can't walk past a painting that doesn't look straight.

[GeekGirl]

The rule of thumb I use is to place the largest possible trace I can. Obviously if you are doing controlled impedance (eg USB data, LVDS, RF etc) then the controlled impedance dictates the width. If you can get away with say 20mils for most of the board, and only need to neck down to say 10mils for around the FPGA, it will make the board more "manufacturable" as you will not have as greater problem with under etching (where the etchent eats under the track).

Years ago it was more of a problem with needing to "balance"  the copper on all the layers, but with modern manufacturing processes, you can have big wide open areas and small tracks.

[David]

This is my preliminary "Final Version 1.0":




Dave

[GeekGirl]

Hi David,

Looks like a great board. Which FPGA are you targeting ?

OK some issues: (constructive

#1 In the 4x6 keypad, what is the track and gap for the brown traces that are horizontal above PB4, 5 etc. (also bellow the leds)

#2 Where the voltages are listed at the top of the board, are the big square pads, tags for a D-Pak voltage regulator ? If so not a good idea to have a hole or via in them (esp not a large one) as it will thief solder during soldering (suck it into the hole) this is mainly an issue for reflow soldering, but it is best to get into good habits

#3  The bus around the Flash, SRAM and bus IF for the PB's / LEDS is very uneaven, this could make for some strange timing issues at high speeds (without seeing the schematic it is hard to say BUT it looks like the PB's and Leds are hanging off the Data bus ?)

BUT once again, good looking board

[David]

Hi David,

Looks like a great board. Which FPGA are you targeting ?

OK some issues: (constructive

#1 In the 4x6 keypad, what is the track and gap for the brown traces that are horizontal above PB4, 5 etc. (also bellow the leds)

#2 Where the voltages are listed at the top of the board, are the big square pads, tags for a D-Pak voltage regulator ? If so not a good idea to have a hole or via in them (esp not a large one) as it will thief solder during soldering (suck it into the hole) this is mainly an issue for reflow soldering, but it is best to get into good habits

#3  The bus around the Flash, SRAM and bus IF for the PB's / LEDS is very uneaven, this could make for some strange timing issues at high speeds (without seeing the schematic it is hard to say BUT it looks like the PB's and Leds are hanging off the Data bus ?)

BUT once again, good looking board

Thanks for the constructive criticism, geekgirl!

1. The tracks for the LED's/Keypad etc are 0.016" wide and use >8mil spacing. The JPEG image doesn't show this very well, I will upload a PDF at some point so you can zoom in.

2. The idea of the large via's under the GND Pads on each voltage regulator was to solder from the reverse side and to allow for better heat dissapation. I am currently looking into revising this as its not necessarily needed.

3. The data bus was the hardest part of the board to route as it it shared between the Keypad, LED's, switches, RAM and ROM. I am not planning on having 'very' high speed designs but this is obviously something that the user will have to consider when designing a core.

Thanks again for the comments,

Dave

[jahonen]

Just a note that even if you would transfer one word per second along that bus, reflections on the bus edge-sensitive control signals could still cause a problem (non-monotonic edges). It is not the data rate which is important, but the edge rate Believe me, that kind of problem is very hard to find

Regards,
Janne

[David]

Its been a long time since I posted here but I've finally had the PCB'S come through 

[TheDirty]

Excellent work David.  It's always interesting to see what goes into peoples board designs.

[David]

Thank you shafri. The PCB's were manufactured by pcbcart.com in China, and they give a very good finish. The lettering is known as Silkscreen and this is created whilst designing the PCB'S. Via's are essentially plated holes through the board and allow the top layer to connect to the bottom layer. The SMD soldering is all by hand using solder paste through a fine nozzle (on a syringe), it is then reflowed using a hot air rework station. It is really a case of time and practice when it comes to soldering! PCB design itself is something of an art and most often takes as much time (if not more) than designing the circuit schematics. I still have a LOT to learn, but its an on-going process.

I recommend you search online for PCB design tips. There's lots out there. Dave has a great document on the basics.

A lot of skill comes from being able to use the design software correctly. I used Eagle PCB, but there's plenty of others out there. Altium Designer (probably the 'de-facto' industry standard) is next on my list to learn!

Dave

[EEwannabe]

Some guy by the name of Dave Jones posted a good tutorial: http://alternatezone.com/electronics/pcbdesign.htm  
Although be warned, I made a board that I was proud of till I read through it, now I don't dare show it around. Thanks Dave!  

- Patrick

p.s. - nice board

[Mechatrommer]

"The PCB's were manufactured by pcbcart.com in China"
well, isnt that take some cost and time to ask someone from china to do and send back to us? if only we can do this from scratch at home.

"plated holes through the board"
dont we need any additional soldering or some type to ensure connectivity between the plated hole and copper plates it is connecting? i used to drill a hole and then insert a piece of wire, solder on top and bottom, as i said, ugly (but i'm happy haha)

"Eagle PCB, but there's plenty of others out there. Altium Designer "
i'm sure i never touch them before. i just use photoshop haha.

"reflowed using a hot air rework station"
i read some components will be easily damaged if exposed to temp more than 150 degree C. i tried that before using hot air, took me ages to melt the soldering just on a particular area, but too long for the components nearby to get exposed to that high temp. maybe something wrong with my skill, sigh. i ended up to just using soldering iron.

"Some guy by the name of Dave Jones posted a good tutorial: http://alternatezone.com/electronics/pcbdesign.htm"
great!!! thanx!!!

thanx david and eewannabe for replying. for other more advanced practitioner, hope my post here dont bored you.

[David]

What are peoples opinions on the routing shown in the attached picture? I know there are right angles where the smaller ceramic caps are connected but I think this is acceptable?




Cheers,
Dave

[TheDirty]

It's impossible to understand how everything is going.  It does not look like your caps are inline with the power output.  Your power caps need to be between the regulator and the rest of the circuit, you can't just branch power off before it goes through the caps, it reduces the caps efficiency tremendously.  Power In -> cap -> regulator -> cap -> rest of circuit.