| Electronics > Projects, Designs, and Technical Stuff |
| USB JTAG Programmer - PCB Layout Advice |
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| David:
Hi all, I am currently working on a "USB-Blaster" like JTAG programmer as a part of a larger project I am doing. I have found it hard to route the layout as the CPLD used has 0.5mm pitch pins and I dont really want to use lower than 0805 parts (caps/res). Has anyone got some good advice for routing tight pitch components? I am currently working on an FPGA based project (144-pin TQFP) and routing the de-coupling caps alone is a nightmare! I have attached the pics of my JTAG programmer layout (Sorry for JPEG quality): http://biketrialsdave.pwp.blueyonder.co.uk/Blaster1.JPG http://biketrialsdave.pwp.blueyonder.co.uk/Blaster2.JPG Cheers, Dave |
| charliex:
what about putting some of the caps on the other side of the board? |
| EEVblog:
Did you autoroute that? Passive component placement is not optimal around the chips. R7 as one example, and it doesn't look like any of the bypass caps are actually right at the power pins. Probably not a problem in this design, but indicative that placement can be much improved. I assume you'll ground fill the bottom layer too? Remember good PCB layout is 90% component placement. Dave. |
| jahonen:
How many signals you need to route out of your FPGA? If you really want to make it good (especially with that 144-pin TQFP one), then forget 2-side PCB and go for 4-layer. Then you can use internal layers for ground and VCC planes alone. Makes your job much easier and gives much better results if you care about EMC and signal integrity (like I do very much even on my hobby projects). BTW, that was not very easy even with 0402-sized caps and 6 layers, still the capacitors were very much PITA. See here. Regards, Janne |
| David:
--- Quote from: EEVblog on January 05, 2010, 02:14:46 am ---Did you autoroute that? Passive component placement is not optimal around the chips. R7 as one example, and it doesn't look like any of the bypass caps are actually right at the power pins. Probably not a problem in this design, but indicative that placement can be much improved. I assume you'll ground fill the bottom layer too? Remember good PCB layout is 90% component placement. Dave. --- End quote --- This was my first go at manually routing the board. The problem I found with putting the caps right by the power pins is that they obstruct the other adjacent pins. I haven't filled the bottom layer but I think that may help, thanks. Dave |
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