VFD Display 101

[NivagSwerdna]

I have eventually given in and bought an IV-18 VFD display to amuse myself with...

I'm planning to use the LM4871 for the filament drive (although MAX628 and uP clock seems feasible) and some kind of boost regulator...

There is a nice reference design here..  http://magictale.com/wp-content/uploads/2015/06/VFD_PSU_EXP01_CircuitDiagram_Rev.1.0.pdf and here https://www.eevblog.com/forum/projects/showing-my-vfd-psu/msg1610392/#msg1610392

Anyway... there seem to be two schools of thought... generate +30V or generate -30V.   I'm tempted to generate +30 (or maybe +35) but many designs use -30...

What is the benefit of using the negative HV?

I obviously need to control the grids and anodes... so anticipating using an HV5812... which pushes me more towards +30?

Hoping for some Rolo and Ian.M replies 

TIA

[Ian.M]

Edit: You cant call it "VFD 101" without linking
https://www.noritake-elec.com/technology/general-technical-information/vfd-operation
which is a must read for any VFD newb.  

Back in the '80's, running a VFD with its filament cathode at a negative potential had considerable advantages - the HT supply would probably be generated by a blocking oscillator or Royer converter driving a pot core or other small transformer, so an isolated filament supply that could be biassed to approx -25V was no problem, and it avoided the need for level shifting for all the anodes and grids, as a VFD doesn't need a lot of current per electrode apart from the filament they could simply be implemented as open collector lateral PNP transistors, referenced to the 5V rail, without any level shifting in an otherwise 5V ASIC, albeit with a large negative substrate bias. 

The development of +HV drivers with integrated shift registers makes the traditional negative filament approach much less attractive, and IMHO you'd be crazy to go down that route unless you were using a LSI VFD controller that required it. (e.g. some sort of retro single chip timer/clock build)

[NivagSwerdna]

It seems LM9022 aka LM4871 is a popular choice... single supply, self-oscillating etc but the output needs to be biased up otherwise on the down side the cathodes will end up more negative than off grids/anodes?

One of the above designs uses a pair of 100R to get a virtual middle and then attaches that to a zenner and C... I put that into a simulator and it seemed to seriously squash the output?

[Ian.M]

Did you try the sim with a pair of current sources feeding a few mA to both ends of the filament to simulate the electron current from cathode to anodes?  Without it the Zener wont be properly biassed.

[Rolo]

I use +HV drivers with integrated shift registers, never worked with negative HV. I use the 20 channel A6812ELW in my designs. They are out of production but can be found on Aliexpress, used several of these and had no issues. I think they are original old stock chips. In case they can't be found anymore they are pin compatible with the Supertex HV5812 and Microchip MAX6921. The A6812 does take 3.3V logic on the inputs, and is cheap.
Is used these in static and multiplex operation, works great. For driving the filament I use the LM4871 and for the HV the LM2733-Y. This design has been posted on this forum. Be ware for fake LM4871's, they work but are not up to the original specs.

[NivagSwerdna]

Thanks. I have a stash of HV5812 thanks to Microchip

My only remaining confusion is how the biasing network is formed.  The schematic shows 10R and 100R, the Zener and 1 capacitor.

I measured the filament of my IV-18 and it comes in at 13.4 ohms, and I think the frequency of the oscillator is 25kHz.

I really need a decent model so I can simulate this but I'm not a frequent spice user, nor am I familiar with biasing.

[Ian.M]

The Magictale design produces -HT of -24V for the VFD and biasses the filament at one end via the 1K, 10K potential divider to approx -21.8V at no cathode current.  However the bias network presents a Thevenin resistance of  909R so at the max rated 10mA Ik, the bias will shift positive by about 9V (neglecting any drop in the -24V -HT rail).   Its not exactly optimal but does provide an example of capacitor coupling the LM4871 filament supply to allow bias to be applied.  N.B. for +HT and +bias, reverse the coupling caps.

Rolo's design also has a capacitively coupled filament, however I believe his schematic has the coupling capacitors the wrong way round, as the LM4871 outputs are on average negative with respect to the bias voltage.    If you are going for approx 5V bias, you don't need a Zener,  just return the CT of the 100R, 100R potential divider across the filament to the +5V rail.   With 100R resistors in the bias divider, its Thevenin resistance is only 50R, so at 10mA Ik, the bias only shifts positive by a negligible 0.5V.

I have a few ideas for how to do adjustable cathode bias, but IMHO fixed 5V bias is probably good enough for most applications as long as the peak filament drive voltage is well under 5V.

[niekvs]

You may want to check out the PT6312BLQ, they can be had for about 0.35$ on AliExpress, and are excellent VFD drivers. I've used them in my design with good success, but indeed it needs a negative supply.

https://www.aliexpress.com/wholesale?ltype=wholesale&d=y&CatId=0&SearchText=pt6312blq&trafficChannel=main&SortType=price_asc&groupsort=1&page=1

Datasheet:

https://pl-1.org/getproductfile.axd?id=5861&filename=PT6312+BLQ%28VT6312%29.pdf

[NivagSwerdna]

PT6312BLQ

I can see some merit although a bit unobtainium perhaps, also my IV-18 has 9 Grids and 8 Anodes.
Tell us about your filament drive and bias... 

[Ian.M]

Another reason to go for -HT would be  if you were building a LSI logic clock or similar, and were having difficulty obtaining parallel input VFD drivers locally, so were planning on using discrete drivers.  You could drive common emitter PNPs direct from the logic with a single base resistor for CMOS logic (as its output is rail-to-rail) or a potential divider to guarantee cutoff if using TTL.  It would also need pulldown resistors to -HT on each PNP collector, In comparison with a +HT VFD supply, you save a transistor and diode in each driver.

[NivagSwerdna]

...like the MPSA55 idea at.. https://threeneurons.wordpress.com/vfd-stuff/
MMBT5401LT3G perhaps?

I think I might be challenged in the i/o department so the advantage of some serial shift latch gadget makes sense rather than discrete... but definitely feasible.

... I am still curious of the biasing... if you look at the first circuit in the original post it has a 10K/1K divider as the bias to one side of the filament... I think you were suggesting above similar network up to +5V... the 100R values just seem too low....?

PS
The polarity of the caps is the same in the first circuit.

[Ian.M]

The 100R resistors in the potential divider are across the filament to provide a virtual center tap to bias it.   They are a tradeoff between wasted power (from the filament driver) and excessive shift in cathode bias potential with varying Ik.  For an IV-18 which runs at about 8mA Ia with all segments of selected digit lit, you could go up to 330R without exceeding 1V variation in bias between two segments lit and all lit (i.e between '1' and '8').  A blanked leading digit would shift the bias by 1.3V but as all segments are off, that wouldn't produce a noticeable brightness difference the way the bias shift between '1' and '8' could.  However the 11mA grid current would already contribute 1.8V of cathode self bias, which goes away during grid blanking if the coupling capacitors to the LM4871 aren't large enough to maintain the bias during inter-digit blanking.

An alternative would be a diode from each end of the filament to the Zener, so the positive swing is clamped at Vz + 1 diode Vf, and using a slightly higher voltage Zener (by half the peak filament drive voltage).   That would have much lower losses, and better bias voltage control.

[NivagSwerdna]

Do I need current limiting R on the grids and anodes?  Some designs seem to have them... others do not??

[Ian.M]

That would depend on the specific VFD.  In general VFDs are designed to be self-limited so that if you apply the rated voltages to filament, anodes and grids, you wont exceed the max permitted anode or grid currents, and if multiplexed with a duty cycle appropriate to the number of digits, also wont exceed the grid or anode dissipation design limit (which may be omitted from the datasheet).  If you are running a multi-digit VFD without multiplexing during development (e.g. if debugging the MCU freezes the multiplexing), it would be advisable to reduce the HT supply so that the brightness of the selected digit isn't significantly higher than it would be if multiplexed.

[NivagSwerdna]

So the datasheet assumes that it is multiplexed and in the case of an IV-18 that a digit is only on 1/9 th of the time?

[Ian.M]

That's likely as there is really no other way of using it effectively, but as I have been unable to find a copy of the original Sovtek ИB-18 datasheet, I'd be extremely cautious.  There are various somewhat contradictory translations of parts of it around under the transliterated Latin part numbers IV-18 and possibly IW-18, but without the original to compare with and maybe some assistance from a Russian speaking technician, as I don't have hands-on experience with this particular VFD, I cant make a definite statement.

I am suspicious about the filament voltage specs - there seem to be different numbers out there.   For initial experiments I would recommend bringing up the voltage slowly till a filament current within the nominal range is obtained.

Its obviously designed for 1/9 duty cycle multiplexing.  Driving it with 1/8 multiplexing, ignoring the symbol digit is unlikely to be a problem, but IMHO it would be a bad idea to use it in a clock with 1/6 multiplexing at full rated anode voltage without PWMed or duty cycle based brightness control.

[NivagSwerdna]

Awaiting my PCB from Elecrow now... went for cheap postage so will be a while.   

[niekvs]

PT6312BLQ

I can see some merit although a bit unobtainium perhaps, also my IV-18 has 9 Grids and 8 Anodes.
Tell us about your filament drive and bias... 

Unobtainium..? Just check that link, many sources for this chip, and at least 10x cheaper than those HV5812s

https://www.aliexpress.com/wholesale?ltype=wholesale&d=y&CatId=0&SearchText=pt6312blq&trafficChannel=main&SortType=price_asc&groupsort=1&page=1&switch_new_app=y

Filament drive is similar as in the first link of the OP.

[NivagSwerdna]

PT6312BLQ seems like a really nice chip but I have been brainwashed by the Microchip samples program.    Might give a PT6312BLQ is I ever get to v2 of this project.
My definition of obtainable is "Farnell stocks it" 

[NivagSwerdna]

Well I assembled my driver board and I'm not 100% happy... the display is multiplexed across the 9 digits... I have a 27kHz interrupt and follow a pattern of 1 blank, 29 display across the 9 digits... i.e. 100Hz per digit.  The Filament drive seems to work OK and the HV measures 34.8V which is close to my design target.
It seems I need to increase the Grid Voltage quite significantly... 50V? 60V? (And that requires a re-design of the HV PSU as my TP61175 will only take me to 38V)

[Rolo]

What are you not happy about?

Verstuurd vanaf mijn ONEPLUS A3003 met Tapatalk

[NivagSwerdna]

What are you not happy about?

It needs to be brighter.  It is hard to show in a photo but in daylight the digits are not distinct enough.  I think I need to pump up the volume.
I'm wondering if I should actually drive the filament harder... Currently measuring 3.2VAC across the filament.

[NivagSwerdna]

I upped the filament voltage and now at 4.7VAC...  definitely think it's a bit wimpy though... looks like I need a 50V design

(A google suggests not all IV-18s are identical https://hackaday.io/project/2360-iv-18-arduino-clock/log/18373-two-version-of-iv-18 ... some look quite transparent... some, like mine have a reasonably solid internal structure,... and some need more grid voltage than others...)