So, I'm back.
Finally had the time to go in details through your suggestions, but I am afraid useful as they all are, I find them not perfectly appropriate (pardon my french).
The project is sciency indeed, as much as it is developed by scientists (HEPPhys are just working on the detector part), but there is strong chance for commercialisation, and I am not sure how much details I can disclose.
To start with, the readily available lab suited solutions will not work. The system I am developing, except the much lower price, needs to be autonomous, provide incessant operation and be extremely rugged. E. g. shock resistant and to operate in >40 C constant ambient temperatures. Each channel (2xPMT) should fit in a toothpaste tube, (if it could fit in the tube tap, the better... but I guess that is too much to ask

)
@daqq,
Are you making something like this maybe?
maybe, it is too hard to tell

@Marco, the reference to TI's TDC7200 is very nice, what worries me is the minimum time between STAR/STOP1 pulse of 12 ns, and between STOP1/STOP2 67 ns (?!?) even if the resolution could be as good as 55 ps, still the necessity of introducing so much delay will bring additional uncertainty that I try to avoid.
Bellow, I will post a schematic of my intentions in order to reply to all those questions regarding the functionality.
What must the master switch do with the signal?
He wants to switch the signal from the lagging PMT, which can be either one, through the delay line.
And then? What is the final goal? Does that switch need to measure the time differences? Some other processing?
If the goal is to measure the delays between pulses and use low cost (off the shelve) hardware then I'd look at CERN's White Rabbit project and their FMC carrier boards. ...
Yep, the goal is to measure the time difference in the interval 0.3-10 ns. No other processing at this stage than determining which pulse comes first. Thanks for the suggestion.
Will need to go more thoroughly through this WR project before commenting it.
Attached is the conceptual schematic of the FE, signal is completely asynchronous so I need to trigger on the lead PMT it could have rep-rate of MHz to mHz (mega to milli). From left to right: PMT, Comparator with hysteresis (ADCMP582 used as a Schmitt) splitter buffer (SB - ADCLK9xx), Master Switch (MSw) which sets the logic configuration of a cross-point switch (CPSw) the lead signal is set to enable SAMPLE of the S&H, the second signal goes through a delay as a HOLD, the delay is to compensate for the lag in the SAMPLE switch (1-2 ns).