De-capping & circuit analysis of hybrid modules

[D Straney]

Thought it was time to do some more detailed reverse-engineering on the various ceramic hybrid modules I've opened:

Analog Devices HTS-0010SD Track and Hold


Here's the datasheet.

This is a fairly high-speed "track and hold" (/ "sample and hold") circuit, which can rapidly sample an input waveform - commonly used as part of an analog-to-digital converter, or to downconvert a high-frequency signal for slower processing.  This one has a bandwidth of 60 Mhz (17 ns period) but needs about a 10 ns sampling window for the output to settle within 1%, so the usable frequency for a sampling oscilloscope, for example, would be more in the single-digit-Mhz range.

Here's how the internal components are divided up, and the complete schematic I traced from a microscope photo:


Most of the large squares are actually capacitors (two horizontal plates separated vertically by a thin dielectric), used for local filtering of the many power supplies.

Input buffer
This section buffers the incoming signal to drive the sampler.  The signal drives two complementary sections, whose outputs are then re-combined by R7, to produce an output which can actively source and sink current.  Having the sequential emitter-followers with an NPN followed by a PNP (and a PNP followed by an NPN) roughly cancels the DC offsets from each transistor's Vbe, if biased correctly.  I wouldn't expect the linearity to be great, as the Vbe values would change depending on load current, but the datasheet shows 0.01% non-linearity for a 1V max. input: the low signal voltage compared to the supply voltage (small change in bias current) and low output current required due to small hold capacitor value & high-impedance output buffer must help a lot.

Sampling bridge
This is a standard 4-diode sampling bridge: I can't find any references that explain their basic operation well, but the idea is that you forward-bias all the diodes (with a current source) to turn them all on.  Because the diodes are intentionally matched to each other, D1 and D4's forward voltages are roughly equal, and D2 and D3's forward voltages are roughly equal, so the output voltage at R9 & hold capacitor C6 follows the input voltage at R8.  To turn off the "gate", you reverse-bias all the diodes, and now hold capacitor C6 is isolated from the input signal, and stores its voltage "indefinitely" (with practical limits).

Bridge driver
This section generates the forward-bias currents and reverse-bias voltages to rapidly switch the sampling bridge on and off, controlled by an ECL input.  The one actual IC in this module is an ECL buffer (or gate with hard-wired input?), which accepts a single ECL input and generates complementary ECL outputs, to drive each side of the sampling bridge separately.  (While on, the cathode-side D1/D4 voltage needs to be low, while the anode-side D2/D3 voltage needs to be high, to turn on the diodes, and vice versa for when the sampling bridge is off)

Q8 and Q11 serve as biasing for a pair of fixed current sinks (Q6 & Q7), and a pair of fixed current sources (Q9 & Q10).  The two halves of Q5 (Q5A & Q5B) serve as switches for the current sinks.  When Q5A is off, for example, Q9 sources current / connects a positive voltage to the top side of the sampling bridge.  When Q5A turns on, it connects Q6, which now (presumably) sinks more current than Q9 is sourcing, and so overall sinks current / connects a negative voltage to the top side of the sampling bridge, instead.

The speed of the sampling bridge driver is a big limitation on the speed of the whole sampler, along with the properties of the sampling bridge diodes themselves, and so to get the most out of the sampler, the switching needs to happen quickly.  The use of ECL and current sources throughout helps here because of...
1. No transistors are ever in saturation, which means that the "storage time", a significant typically-µs-scale delay when bringing a bipolar out of saturation, doesn't slow down switching.
2. The fixed currents, if set to sufficiently high values, rapidly charge or discharge the various parasitic capacitances at the switching nodes.  This provides a simple "control knob" the designer can use for selecting a tradeoff between power consumption and switching speed.
This was the standard way of doing high-speed digital switching with bipolar transistors before fast MOSFETs and CMOS logic became common a decade or two later.

Q5 is a 5-transistor array, with the same pinout & arrangement as a CA3045/CA3046 or CA3086: 3 individual transistors, and 2 connected as a differential pair.  However, surprisingly, only two of the 5 are actually used.  I don't know why they didn't use a 2-transistor matched pair for this.


Also, one mystery here is the DC behavior of the bridge driver.  With AC-only coupling via C1 & C2, only short excursions from the default state (whether track, or hold) would be allowed, and I didn't see any mention of that in the datasheet.  Also, the only valid states for the sampling bridge are with Q5A & Q5B in opposite states: having both halves of Q5 off when idle doesn't make any sense (although R15 might have something to do with that).  I think what looks like capacitors here in the bridge driver (C1 & C2) might actually be diodes for level-shifting between the -5.2V of the ECL signals, and the -15V for the rest of the bridge driver.  I can't come up with a diode configuration which actually makes sense though (even including Q5 being PNPs instead of NPNs).

Output buffer
Q12 is a JFET used to buffer the hold capacitor's value; a JFET is used here instead of a bipolar transistor because of its infinitesimal input leakage current drains the tiny hold capacitor's voltage much slower than a bipolar's base current would.  After Q12A's buffering of the hold capacitor voltage, this drives a class-AB output stage with Q14 & Q15 creating an offset voltage to compensate for Q16 & Q19's Vbe, and create an appropriate DC collector current through Q16 & Q19 at zero voltage (to avoid excessive crossover distortion).  Q12B and Q13 create a current sink to bias Q12A and Q14/Q15 at a constant current.

Just like the input buffer, with no feedback you'd expect the output buffer's linearity to suffer here as the Vbe values change with changing current, ruining the careful balancing act, and that's reflected by the datasheet.  With a 1KΩ load on the output, harmonic distortion is listed as -68 dB, but with a much heavier 75Ω load, this drops to -50 dB.  Honestly, these are still impressive numbers overall for such a simple circuit (esp. because this includes the distortion of the input buffer & sampling bridge), and this is not to criticize the design - just to illustrate the limitations and tradeoffs.

Here's Q12, a matched pair on a single die:


Feedback
At first when tracing the circuit, I thought this might be some sort of compensation for various parasitic effects of the sampling bridge.  However, on further study, this is actually a part of the bridge driver!  Q17 and Q18 create a copy of the output voltage (and therefore, a copy of the hold capacitor voltage) at R10.

Remember how I said that the transistors in the bridge driver never were put into saturation?  Without this section of the circuit, when the sampling bridge was turned off in "voltage mode" to reverse-bias the sampling diodes, both Q9 and Q7 would be in saturation: there's no path for collector current after charging the parasitic capacitances, and so their collector voltages would rise(/fall) past their base voltages.  However, D5, D6, and R10 ensure that Q9 and Q10 always are in the active region by providing a path for their collector current, and limiting how far their collector voltages can rise or fall.  R10 sets the reverse-bias voltage on D3 & D4, as (fixed current) x (resistance).

Closing
Finally, the weird silicon(?) resistors make for some interesting shapes:


Let me know if you have any insights or questions.

[D Straney]

Clarification on the "feedback" section of the circuit:
D5, D6, and R10 make the sampling bridge's off-state voltages referenced to the hold capacitor voltage.  The D1 & D4 cathodes will always be "X" volts above C6, and the D2 & D3 anodes will always be "Y" volts below C6, etc. with "X" & "Y" determined by the bridge driver's fixed current source & sink values multiplied by each half of R10.

Besides keeping Q9 & Q7 out of saturation, I think the biggest reason to do this is actually for the bridge's turn-off & off-state behavior.  When the control voltages on the sampling bridge are flipped to reverse-bias D1-D4 and close the gate, the rising voltage on D4's cathode injects current into C6 through D4's parasitic capacitance.  At the same time, the falling voltage on D3's anode pulls current out of C6 through D3's parasitic capacitance: a simple matter of dV/dt across a capacitor.  C6 has a very small value, to allow it to sample the input signal quickly (short gate-opening times) and give it a large analog bandwidth (input buffer is limited in slewing a large capacitive load quickly), so these currents can introduce some serious error into the C6 voltage.

However, because the final D4-cathode and D3-anode voltages are fixed relative to C6's voltage, and D3 & D4 are the same type with the same parasitic capacitance characteristics, the total charge injected into C6 at turn-off through D4 is going to be almost exactly equal to the charge removed from C6 through D3.  The two errors in opposite directions cancel out.  Otherwise, if the final D4-cathode & D3-anode voltages were fixed at, let's say, +10V & -10V, it means that positive output voltages would see a consistent negative error (more charge removed by moving D3's anode a larger "distance" from Vout to -10V) and negative output voltages would see a consistent positive error (more charge injected by moving D4's anode a larger "distance" from Vout to +10V).

During the off-state, having equal reverse-bias voltages across D3 & D4 also means that the leakage currents through both of them will cancel out, therefore removing another source of error which would cause C6's voltage to drift over time.  This is especially important with the Schottky diodes used in the sampling bridge: the tradeoff vs. plain P-N junction diodes is lower forward voltage and no reverse-recovery effects, for higher capacitance and higher leakage.  The D5/D6/R10 "equal negative bias" scheme here takes care of both the capacitance & leakage effects all at once.

[David Hess]

I am surprised that it is not faster.  The sampling time in this type of design is primarily limited by the RC delay of the driver and load capacitance.

[schmitt trigger]

The 8518 label in the lid must be likely the date code?

Do you know where this track and hold device came from?

[D Straney]

The 8518 label in the lid must be likely the date code?

I agree, think that's right.

Do you know where this track and hold device came from?

An eBay batch of (unused) NOS parts, that this guy got, and was kind enough to give one to me as part of a two-way duplicate swap.  It's a standard COTS part, rather than anything application-specific.  So I don't know exactly what specific pieces of equipment used this internally.

I am surprised that it is not faster.  The sampling time in this type of design is primarily limited by the RC delay of the driver and load capacitance.

Me too!  Especially with the ECL input I was expecting some couple-ns kinds of times.  Thought it was interesting that they advertised the 5 ps jitter in the sample window timing, but the slow settling time and long sampling window needed make that less impressive in practice than it sounds - unless you're going for serious precision on a slower signal, like if building a precision multi-Mhz LVDT for some reason.

[D Straney]

Teledyne C66-1 Solid-State Relay
This comes in a metal can:

Now with lid removed:

There were a couple blobs of epoxy (one over the top-left electronics, and one over the top-right electronics) that I removed to get these photos.  Removing the epoxy moved the wirebonds, so don't pay too much attention to where the wirebonds sit in the upper half.


The output switching is done by the two big power transistors in the bottom half: these are arranged back-to-back, so that the body diodes never conduct at the same time, with a shared source connection that runs up the middle between them.


These power MOSFET gates are driven optically.  The isolated control side consists of two LEDs connected in series in the top-right corner (the two tiny squares), and these shine light on a photovoltaic array right next to them (the larger square).  I'm not sure if the light is passed sideways across a small horizontal gap, or whether the light was diffused and reflected through the white epoxy blob (from LED top surface to PV top surface) to add horizontal electrical insulation.

The LEDs & mini solar cell generate a gate voltage to turn on the power MOSFETs, but the current these can produce is very low - discrete versions of PV isolators can only produce 10s of uA, from an LED current of 10s of mA.  This charges the power MOSFET gate capacitance slowly, but multi-ms turn-on times or 10s-of-ms turn-on times are fine if you're just switching a load on and off, and not trying to do 100+ kHz switching for a power supply.  However, this is a problem for turn-off: the pull-down resistor on the MOSFET gates, to discharge the gate voltage when the input drive voltage isn't present, needs to be large enough to avoid stealing all the turn-on current, but this makes the turn-off even slower than the turn-on.


There's also an IC on the power side; I accidentally took a chip out of it with my knife while trying to carefully peel away the epoxy, so although it's pretty simple, I can't fully map the circuitry.  This is probably responsible for some kind of "fast turn-off" function, to sense when the gate voltage starts to sag as the LEDs are turned off, and actively discharge the gate capacitances for a faster turn-off.