Using a 74F269

[DMartens]

Have a 74F269 8-bit counter wired up as attached ... goal is to make it count up or down to a certain value ... making /PE permanently high or connecting it to /TC has the same result: the counter endlessly counts 0..255 and the /TC output gives a short pulse every 256 counts ... so I can't get it to count up to (or down from) whatever number I have put on its Px inputs ... based on the Function Table (attached), I expected that connecting /TC to /PE will (re)load the Px values every time the count reaches up to 255 or down to 0 ... I googled "sample circuits with 74F269" but nothing useful comes up ... how to connect the /PE pins so it loads and counts up/down from there? .. thanks

[iMo]

.. the counter endlessly counts 0..255 and the /TC output gives a short pulse every 256 counts ...

With 1MHz clock (best 50% duty to avoid issues) the negative pulse at the /TC shall be 1usec long - is that the case?
In your wiring it seems indeed the counter shall load 170 with the rising edge of clock while the /TC is low and then it counts up till 255, so the period is perhaps 85usecs.
PS: also it is a 5V device (power hungry ~100mA) so it will not work properly at 3.3V, for example..

[jwet]

The 74F269 is "fully" synchronous meaning that the load is also only done on a clock edge.  The TC output is gone by the time the rising edge of the next clock comes- this wrap around won't work.  The load has to be there 6 ns before the clock rises.(setup time).  You could add a flip flop to capture TC for an extra count or kluge up something with an RC, etc depending on what you're doing.

This '269 function never made it over to the HC families.  If you don't need the 100 Mhz, F logic is messy stuff.

There are several presettable counters in the HC series- unfortunately no 8 bitters.  HC can toggle at over 20 Mhz at a 6v supply, something like 15 at 5v.  The '193 is a 4 bit up down with asynchronous load and some borrow logic for cascading.  These can be cascaded to 8 bits with some minor limitations.  See the TI '193 datasheet, it has the cascaded circuit.  These parts have dual clocks- one for up and one for down- kind of screwy. This is sort of necessitated by having a sync up and down. Might be something else to work around.

If you don't need up AND down, the 74HC161 is pressetable and but up only and has a async clear and load.  Look at the data sheet for cascading.

Have fun.

[Benta]

The 74F269 is "fully" synchronous meaning that the load is also only done on a clock edge.  The TC output is gone by the time the rising edge of the next clock comes- this wrap around won't work.

I disagree. The TC output is valid for a full cycle and will be present at the next rising clock edge.
More likely that the OP is trying to clock it at too high frequency.

[jwet]

Benta, you're right but F logic is good to 100M and he shows 1Mhz.  Perhaps it a hold time issue though its shown as 0.  F logic is terrible.  This one chip will burn up a half watt just sitting there.

[tggzzz]

One of the problems with FTTL is that the output can source sink a lot of current and the transitions are fast. In the mid 80s and even on PCBs with normal decoupling, that became a problem when several outputs were switching simultaneously, especially when driving transmission lines or above normal capacitance.

The cause was the currents during the transitions caused ground bounce inside the IC. For simple buffers that manifested itself as crosstalk, glitches and increased delays. For circuits containing state (registers, counters), the state could be flipped. The TC is a combinatorial output derived from all the counter outputs. The OP mentions TC giving a "short pulse", but doesn't compare that to the clock period. It is thus possible that internal ground bounce is flipping some/all counter outputs asynchronously, which would mess up the preset operation.

The OP hasn't mentioned the construction techniques. Since even PCB construction are known to be problematic, if he is using a solderless breadboard then I doubt he will get this to work as expected.

For the avoidance of doubt, any such problems would occur even with a 1Hz clock. The clock frequency is irrelevant, only the transition time and lead inductance is relevant.

[Benta]

@tggzzz:  +1
74F is probably one of the worst logic families to work with. Fortunately obsolete since 25+ years.
@OP: go with two 74AC161 or 74LVC161 types instead. Currently available.
And use a perf board. Solderless breadboards are for kids.

[PCB.Wiz]

If the OP only needs TC, there is also 74HC40103 8 bit down counters, single package.

[jwet]

This is funny, the OP is silent and a bunch of very experienced guys are exchanging really good ideas and working overtime.  Take care guys- I appreciate your input and learned a bit...

[Benta]

and learned a bit...

That's the important part.   

[DMartens]

hi all ... thank you for your insights and advice ... and apologies for being quiet ... I was away all weekend for a family gathering.

Turns out the chip works just fine as per my schematic ... I just had not connected the Px inputs to GND ... I had assumed that leaving them unconnected, they would be all zeros (yes ... I know ... silly me) ... after connecting them all to GND, the chip now performs as expected.

Really appreciate the insights and comments on the F-technology ... I did wonder why it is not that popular ... your comments explain the hows and whys ... will change my design to a different logic family ... not sure which one yet but your comments have provided some good alternatives.