How IC's are designed?

[Michael George]

I watched on YouTube the manufacturing process of IC's and I would like to learn how IC's are designed. What is the best software that is used in large companies?

In case of designing a very complex IC such as a processor or a smart phone chip, What do engineers do? Do they draw a large schematic on a software that contains logic gates? Do they draw every single NAND gate  ?

Thank you very much,

[Fungus]

Most of the circuitry inside ICs will be built up from smaller blocks. You design the blocks and you can replicate them all over the place.

A good example is a RAM chip. RAM chips can have billions of transistors but you only need to draw one memory cell and the rest is just replication via copy/paste.

Similarly buses: An adder might be 32 bits wide but you only need to draw one adder and the other 31 lines are copy/paste. A large ALU can be built up quite quickly this way,

Graphics chips? There's a lot of floating point adders and multipliers in there but you only have to draw one of them.

But ... a lot of the work these days isn't done by "drawing". Most people use some form of HDL ("hardware description language") to describe buses and interconnections then a compiler generates a circuit with the actual NAND gates.

Start your journey into HDLs here: https://en.wikipedia.org/wiki/VHDL

[T3sl4co1l]

"Most" means digital CMOS, by a huge margin.  That will be HDL.

If you mean analog as well, that starts with simulations -- driven by SPICE models provided by the manufacturer, under strict NDA/license of course -- and proceeds with a large amount of virtual testing (note that digital requires even more testing, because you can't even begin to hope to test all possible input/output and internal states in a nontrivial design!), before moving to layout and finally fab (and a final round of testing).

AFAIK, Cadence has a sizable fraction of the market in a lot of the software involved.  If you have to ask the price, you can't afford it.

Tim

[T3sl4co1l]

I haven't heard anything about them, or any of the professional tools for that matter...

[filssavi]

AFAIK, Cadence has a sizable fraction of the market in a lot of the software involved.  If you have to ask the price, you can't afford it.

Do you think ElectricVLSI or Tanner are good ideas? I learned Cadence from university, but apparently if I am to start a business, I cannot afford Cadence at all.
My main focus is on 0.35um/0.5um CMOS/BiCMOS analog or mixed signal. High performance digital is not my specialty, nor high voltage. Tu n

I'd say that for analog having a good simulator (which means either synopsis or cadence) is not optional, it is required, at 0.35 um you are already have short channel devices, so hand calcularion wil be off by quite a bit, also the pasdives in a integrated circuit are far from perfect so simulation is required

Now simulation are only as good as your model is, and to have a good model you need to get it from the fab itself, the fab (after signing NDA with your company no single peoples) will give you a PDK (process developement kit) wich is a big obfuscated blob you plug in cadence(or synopsis) simulator and it spits out results

If you can get  simulation models for your eda suite of choice you also need to decide wether the money saved by using the cheaper cad are worth the risk of having to do more prototype runs because the simulator is less accurate

Depending on your Financial situation you might also considerazione taking out a loan to start the company with which you can get a cadence/synopsis licenze of if it is to far you might give tanner/Electric a shot, knowing that it is not so proven and it might bust some production runs

[T3sl4co1l]

Tools are no substitute for good modeling.  I know of a guy who's been using PSPICE basically since it was introduced (I think?).

Tim

[kfnight]

AFAIK, Cadence has a sizable fraction of the market in a lot of the software involved.  If you have to ask the price, you can't afford it.

Do you think ElectricVLSI or Tanner are good ideas? I learned Cadence from university, but apparently if I am to start a business, I cannot afford Cadence at all.
My main focus is on 0.35um/0.5um CMOS/BiCMOS analog or mixed signal. High performance digital is not my specialty, nor high voltage.

If your company is a startup then many EDA companies will offer (substantial) discounts in using their tools. The main reason being that if your company should get big, you will need to buy lots of licenses at full price. Otherwise it would be nearly impossible for a semiconductor startup to get off the ground if they had to pay millions of dollars up-front to use the tools. As an example see

https://www.mentor.com/company/partner_programs/tfs-program

[Berni]

Depends what sort of IC it is. An analog chip like a op amp would be mostly drawn trough a schematic that then gets lain out out much like a PCB except that the components are prebuilt silicon masks and the software to do it is specialized for it. When you get to fancy RF chips things get more involved with fine tuning the actual parts, tons of simulations etc.

But when it comes to digital chips things start having a lot in common with FPGAs. They use the same languages like VHDL or Verilog to program in the behavior of the chip. They will often compile it and load it inside a FPGA for testing to make sure it works well before they start the expensive process of turning it in to a actual chip. Again specialised software is used to compile that HDL language in to a set of transistor libraries(they are more like gates at that point) that then again get layed out similar to a PCB but with a lot of auto router help(Wiring milions of gates would obviously take a while by hand).

If you want to see how digital chip design was like in the old days you are in luck cause someone made a game out of it:
http://www.zachtronics.com/kohctpyktop-engineer-of-the-people/



To give it some story its set in Soviet Russia where you start off as a novice IC designer with basic gates, moving on to adders, counters, shift registers etc. finnaly ending up making SRAM, ALUs and some military "ASIC" chips that tie in to the story.(And try not to get too much in to it as it can be a massive time sink when it tingles your engineering cravings)

[wraper]

If you want to see how digital chip design was like in the old days you are in luck cause someone made a game out of it:
http://www.zachtronics.com/kohctpyktop-engineer-of-the-people/

Part numbers completely wrong, not according soviet/russian way of assigning part numbers. KTxxx all would be silicon transistors, not IC's. KCxxx would be zeners, KDxxx - diodes. Some others do not exist. Kxxx, KRxxx, KMxxx - would be valid, but not for military.

[Berni]

Part numbers completely wrong, not according soviet/russian way of assigning part numbers. KTxxx all would be silicon transistors, not IC's. KCxxx would be zeners, KDxxx - diodes. Some others do not exist. Kxxx, KRxxx, KMxxx - would be valid, but not for military.

None of it is actually all that realistic. The whole concept is massively simplified down in order to make it easy enough to be a game, although it can get plenty complex as things get bigger. For example there is no ground anywhere, just Vcc, delays only count on junctions, the actual transistors work both ways in all aspects unlike real ones etc. But its just detailed enough to convey the core concept of oldschool IC design.

[helius]

You can do worse than reading one of the classic books on the topic, like Introduction to VLSI Systems or CMOS VLSI Design. These days, chips are built from macrocells and even larger function blocks, but the code that synthesizes each block has parameters to tweak for speed and power consumption. By far the most critical task of designing a large IC is clock distribution, since there will be major skew over a large area.

[Berni]

You can do worse than reading one of the classic books on the topic, like Introduction to VLSI Systems or CMOS VLSI Design. These days, chips are built from macrocells and even larger function blocks, but the code that synthesizes each block has parameters to tweak for speed and power consumption. By far the most critical task of designing a large IC is clock distribution, since there will be major skew over a large area.

I was always impressed how bravely FPGAs do things with no setup and hold times where the signals are sampled on the same clock edge that it changes on, doing things like that outside a chip on a PCB tends to end in disaster.

[coppice]

AFAIK, Cadence has a sizable fraction of the market in a lot of the software involved.  If you have to ask the price, you can't afford it.

Do you think ElectricVLSI or Tanner are good ideas? I learned Cadence from university, but apparently if I am to start a business, I cannot afford Cadence at all.
My main focus is on 0.35um/0.5um CMOS/BiCMOS analog or mixed signal. High performance digital is not my specialty, nor high voltage.

That sound like a coarse, high cost, geometry to be starting new work with in 2016.

[langwadt]

You can do worse than reading one of the classic books on the topic, like Introduction to VLSI Systems or CMOS VLSI Design. These days, chips are built from macrocells and even larger function blocks, but the code that synthesizes each block has parameters to tweak for speed and power consumption. By far the most critical task of designing a large IC is clock distribution, since there will be major skew over a large area.

I was always impressed how bravely FPGAs do things with no setup and hold times where the signals are sampled on the same clock edge that it changes on, doing things like that outside a chip on a PCB tends to end in disaster.

it does? first, you can't have no hold and no setup at the same time

with zero (or sligthly negative) hold things are easy as long as you can rely on time only going forwards

data can't possible change until after an edge, your data is always from before the edge. All you
have to do is make sure the clock arrives faster than the data, ICs usually have more delay than tracks
and you can  route the clock in the opposite direction of the data to make sure

[helius]

I was always impressed how bravely FPGAs do things with no setup and hold times where the signals are sampled on the same clock edge that it changes on, doing things like that outside a chip on a PCB tends to end in disaster.

The way that FPGAs are meant to work, you have no choice but to go through a latch to get from one slice to another; it's fully static. The whole thing is divided up into little bits that are all synchronized, which has negative performance implications. Generally there are ways to configure the slices to be transparent to the clock but the vendor tools will never do that.

data can't possible change until after an edge, your data is always from before the edge. All you
have to do is make sure the clock arrives faster than the data, ICs usually have more delay than tracks
and you can  route the clock in the opposite direction of the data to make sure

Or use asynchronous signal encodings.