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Using UART TX line to supply power when idle
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sebmadgwick:
The attached schematic and screenshot is about as good as the 2 inverter + MOSFET solution will get.  The falling edge is delayed by 90 ns.  Not ideal for 3 Mbaud.

My original post and suggestion of using paralleled 74LVC125 drivers would use a GPIO to enable/disable power.  If was to go down this route then the solution is a low output capacitance MOSFET (e.g. DMG1013UW-7).  I'm now interested in a solution that is able to source current whenever UART is left idle (high) and so not require GPIO control.  Perhaps paralleled 74-series drivers could be used.


--- Quote from: David Hess on March 20, 2020, 10:39:51 am ---What imbalance are you referring to?  Is that imbalance between paralleled drivers?
--- End quote ---
If current is not split evenly between all drivers then the driver under the greatest load may fail, this would then increase the load on the remaining drivers so that the next driver under the greatest load would fail and so on.  This is what I mean by an imbalance causing a runaway failure.
David Hess:

--- Quote from: sebmadgwick on March 20, 2020, 11:46:26 am ---If current is not split evenly between all drivers then the driver under the greatest load may fail, this would then increase the load on the remaining drivers so that the next driver under the greatest load would fail and so on.  This is what I mean by an imbalance causing a runaway failure.
--- End quote ---

That is very unlikely to ever be a problem with CMOS gate outputs because their channel resistance is relatively high.  For instance HCMOS is about 25 ohms at 5 volts.

The output voltage requirements are usually what dictate how many outputs are needed in parallel to reduce voltage drop to an acceptable level rather than the output current requirements.
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