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Vacuum Fluorescent Display Driver

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I have an Agilent 53132A counter with a slightly messed up 12-digit display.

The odd part:

The display is fine during different stages. If I inject 10MHz, the display is fine except the 12th digit, segment C (right bottom vertical segment), remains on (something I could live with), however, if I access a menu, the segment is fine.

Injecting around 15MHz sometimes (I emphasize that word) causes digits four and five to have extra segments illuminated; and the same if I access menu options (AUTO TRIG is displayed as AUTOOTRIG). Other times extra commas and/or periods are displayed in multiple locations (hard to tell if it's trying to show a comma or it's just a bright period) Usually the wrong commas and/or periods are also in the fourth and fifth digit.

I'm not asking for help diagnosing the issue (unless someone has repaired a similar issue), but mainly I suspect the display driver IC (SN75518FN) because the frequencies seem to be correct if I watch the fourth and fifth digit change from correct to incorrect.

The driver chip datasheet (see attached) isn't exactly helpful because I'm unfamiliar with fluorescent displays. The circuit (see attached) uses 32 of the output pins on the chip which correlates to the datasheet. Unfortunately I can't locate the datasheet for the fluorescent display.

My initial assumption was this is similar to a seven-segment display and would be 84 driver lines (7 * 12), but this isn't the case since it's only using 32. My next thought is this is scanning using the internal shift register, but this still doesn't mathematically add.

The reason(s) I'd like to understand this: obviously to learn, but also maybe to use a logic analyzer (I have a 16-channel unit) to confirm the output isn't matching the input data.

Update: looking more, maybe I understood this a bit more than I thought. I'm assuming G1 through G12 activate each digit as the chip scans left to right (or right to left?). Since the chip also outputs SEG-A thru SEG-Q (17 outputs), looking at the display closer reveals each digit is comprised of 14 segments (rather than 7 like I thought), a comma, period, and a dot, this would add to 17.

If this is accurate, can I still measure this on a logic analyzer to confirm the chip is bad, and, how are other things on the display shown such as MHz, freq, per, Ch1, Ch2, etc...?

The display looks (see attached) to multiplex 12 digits with each digit consisting of 18 segments:
  8 line segments (standard a..g) with a split g segment,
  4 diagonals,
  2 center verticals,
  3 colon dots and comma (rightmost digit replaces the dots and comma with annunciators)
  1 annunciator.
I can't explain where two additional driver (SN75518FN) lines are used on the display.

How to drive VFDs can be found here. 

In summary, one digit (grid) line is energized (to +38VDC) along with selected segments of that digit (also to +38VDC); all other lines grounded. Then the next digit (grid) + segments are lit, etc.  Since the driver is just a SPI consumer, expect a stream of 32 bits * 12 * Hz refresh rate.

There is a low AC voltage across the FIL1+FIL2 lines providing a stream of electrons, with the mid-point (split) AC voltage biased (via zener) a few volts above ground so that any grounded driver lines keep that segment or grid off completely (no bleeding from adjacent segments).

I'm not sure which (display or driver) is causing the misfiring segments that you're seeing. This is a known problem and has been documented with other HP VFD products such as the 34401A on this forum. 

You could use your LA to compare the SPI stream with the driver output but be wary of the +38VDC so use a divider.  ie. an unchanging SPI stream should produce a unchanging output line state. If not, the driver is bad.  If true, and the display shows changing segments, then the display is bad.

The display is multiplexed, 14 segments plus colon (DP2), decimal pt (DP1), comma (SEG-COM), annunciators (SEG-COM) and a few others Freq, Gate, Ch1. as simply extra segments per digit.
Segments go positive voltage wrt cathode to light them but digit (screen) grids must also go positive to enable a digit, so the segments can light.
Note the directly-heated cathode (filaments) are biased at 6.2V up. Not to be confused with end-end voltage which is the filament heater voltage. VFD power supply DC-DC converter U30-A outputs +38V and the filament bias I think done by VR1 or VR2 zeners on the main board.
So the VFD sees +31.8V (when '75518 is outputting +38V) at the grid and segments, or -6.2V (relative) (when '75518 is outputting 0V) to bias the VFD into cutoff.
If you get segment or digit overlap or smearing, I would suspect the 75518 but also confirm the cathode bias is OK at +6.2V and the anode supply is around +38V. I'm not sure how that Endcott DC-DC converter module is, what's inside.
Careful the logic analyzer can handle high voltage +38V signals.
You can use a scope and look for the signal swing say 36 to 5V low (@1mA) it has push-pull outputs and can source+sink current.
You can force the issue with the '75518, if it has weak outputs by stressing an output pin by adding load resistor and seeing what the output voltage does. Say a 20k to a VFD pin should not cause much change, either to GND or +38V - if the IC is OK.
Or the IC is switching slow and overlap between digits is what you are seeing.

HV518PJ is in production.


--- Quote ---I'm not sure which (display or driver) is causing the misfiring segments that you're seeing. This is a known problem and has been documented with other HP VFD products such as the 34401A on this forum.
--- End quote ---

Prior I did some research and found exactly what you referred to. I was trying not to guess and just swap without measuring and tried to understand the datasheet.

The explanations are helpful, but wow, still a bit confusing. Does each digit turn on and off rapidly? If I'm thinking about this correctly, let's say it's a four-digit display and 1, 2, 3, and 4, come into the serial input. Is '1' sent on all 17 output lines and the associated Gx output selects which digit to light (the far left digit in this example)? After '2' is received, the '1' digit is turned off, and '2' is shown in the second far left digit? It's done rapidly, so to the human eye it's not noticed?

My logic analyzer (Kingst 16-channel model LA2016 I believe) shows it can handle +/-50v. I'm uncertain how easy this will be to look at the serial data, figure out which bit is the fourth and fifth digit, and then see that it's outputting something other than the bit in the serial data.

The SN75518FN is a 32-bit serial-in shift register with latched outputs. This is similar to a cascade of 4, 74HC595s.

This means that it can receive, via SPI, 32 bits to fill its shift register WHILE the output lines still holds the previous 32 bits steady. The MCU then toggles the LATCH EN pin which moves the serial shift register [internal] outputs into the output latches which will now show a new state on the output lines (all at once). The STROBE input just briefly blanks all outputs (sets to GND) during the transition when the output latches are loaded with new serial-in data (since STROBE is tied to LATCH EN in the schematic).

So, as for your example display, the MCU sends 32 CLKs and DATA, then LATCH EN is toggled (LOW-HIGH-LOW) which causes those 32 bits to now appear on the output lines.  The MCU waits 4.2ms then outputs the next 32 bit digit data stream. After 4, 32bit streams+4.2ms waits, it cycles back to digit 1.  Only 1 grid output is ever enabled at a time otherwise the same segment data will be on in multiple digits.

Why a 4.2ms wait? A: You'll want to refresh each digit at least 60 times per second, so for your 4 digit example that's 4 * 60 = 240Hz or 1/240s = 4.2ms.  In the 53132A with 12 digits, you'll need at least 12 * 60 = 720Hz or 1/720s = 1.4ms wait.  The 32 bit stream needs to be fast enough to complete within one wait, obviously.

See attached Noritake diagram. The serial stream of grids and segments appears as a column (say T1). During T1 time, a new 32 bit stream is sent then transitioned to the output latches during the dotted vertical lines time where all output lines are blanked (GNDed) momentarily before showing T2 state on the output lines.  I think the reason for the blanking is to make sure all digits and segments are completely off so your eye won't perceive a dim segment that was on in the previous digit.


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