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variable frequency square wave
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IDEngineer:
"Arbitrary frequency" and "something like 0.1% accuracy of the frequency control" aren't necessarily the same thing, which is why we've got different interpretations running through this thread.

But OK, let's run with it. Your example of 72MHz timer frequency isn't cast in stone. Remember (using the STM32 in this case), there's a 16 bit prescaler AND a 16 bit preload/comparator. Sometimes to get intermediate frequencies you need to vary both parameters, running the timer at a different frequency so the resulting divide yields the result you seek. We'd have to study the architecture of the STM32's timer system, but this potentially yields you (16 + 16 =) 32 bits of potential resolution off the original clock source to the timer module. Using your example of 72MHz and (to quote you again) "doing some math", that's (72MHz / (2^32) =) 0.017Hz per LSb, which is better than 0.1% resolution (if that's how the OP's comments are now being interpreted) at any frequency above 17Hz, almost two orders of magnitude below his 1KHz bottom end.

ogden:

--- Quote from: IDEngineer on May 24, 2019, 06:10:56 pm ---"Arbitrary frequency" and "something like 0.1% accuracy of the frequency control" aren't necessarily the same thing, which is why we've got different interpretations running through this thread.

--- End quote ---

Arbitrary frequency is what it is - *any* frequency. If you do not understand what "0.1% accuracy of the frequency control" means then I wonder - are we on the same page here?  :-//


--- Quote ---But OK, let's run with it. Your example of 72MHz timer frequency isn't cast in stone. Remember (using the STM32 in this case), there's a 16 bit prescaler AND a 16 bit preload/comparator. Sometimes to get intermediate frequencies you need to vary both parameters, running the timer at a different frequency so the resulting divide yields the result you seek. We'd have to study the architecture of the STM32's timer system, but this potentially yields you (16 + 16 =) 32 bits of potential resolution off the original clock source to the timer module. Using your example of 72MHz and (to quote you again) "doing some math", that's (72MHz / (2^32) =) 0.017Hz per LSb, which is better than 0.1% resolution (if that's how the OP's comments are now being interpreted) at any frequency above 17Hz, almost two orders of magnitude below his 1KHz bottom end.

--- End quote ---

He did not say 0.1% resolution just for bottom end.  :-DD  So please be so kind and do your math for frequency I did mention, 993 KHz. Hint: 72MHz divided by 72 is 1MHz but divided by 73 is... 986 KHz which is 0.68% away from 993 KHz.
IDEngineer:

--- Quote from: ogden on May 24, 2019, 06:35:18 pm ---He did not say 0.1% resolution just for bottom end.  :-DD  So please be so kind and do your math for frequency I did mention, 993 KHz. Hint: 72MHz divided by 72 is 1MHz but divided by 73 is... 986 KHz which is 0.68% away from 993 KHz.
--- End quote ---
You're not getting it. Continuing with your 72MHz example, the 0.017Hz increment is a constant with 32 bits of divisor. I calculated and gave you the minimum frequency that would satisfy his 0.1% error. The error gets increasingly better at increasing frequencies. "Doing some math" again, the error at his bottom end of 1KHz would be 0.0017% and at his top end of 1MHz it would be 1.7^-08%.

EDIT: It appears you need more explicit examples. Using your clock, 72MHz, with 32 bits of resolution means the LSb is 0.017Hz. Your target frequency is 993KHz. Divide that by the LSb and you get 59,234,757.3. This means you need a divisor of 59,234,757. Factor that number into two values that can be represented by 16 bit integers (range 0-65535) and there you are. There's an error of 0.3 LSb, which (if you "do the math" again) you'll discover is well within the 0.1% requested. In fact, an entire LSb is within the spec, which is exactly the point and why you can truncate the fractional part (or, if you want to be really detailed, do proper rounding).
bson:

--- Quote from: dpenev on May 20, 2019, 08:33:06 am ---implementing of fractional divider for 1MHz output will be very difficult I believe.

--- End quote ---
From a 16MHz crystal?  Really?
ogden:

--- Quote from: IDEngineer on May 24, 2019, 06:43:02 pm ---EDIT: It appears you need more explicit examples. Using your clock, 72MHz, with 32 bits of resolution means the LSb is 0.017Hz. Your target frequency is 993KHz. Divide that by the LSb and you get 59,234,757.3. This means you need a divisor of 59,234,757.

--- End quote ---

Divisor 59,234,757 to get what exactly??? 72000000/59234757 =1.2155 Hz. It is way off 993000 Hz I asked for.
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