Via fence configuration to decrease emissions

[ricko_uk]

Hi,
I have a 6-layers PCB with several high speed controlled impedance signals including LVDS, Ethernet, USB etc.

The previous version of the board had EMI emissions very close to the limit. So in this version I am thinking of shielding all high speed signals by sandwiching them between GND plane (layer 3) and GND copper pour (on layer 1). The stackup is:
- Layer 1 = copper flood/pour in red
- Layer 2 = high speed differential (and single ended) signals in yellow
- Layer 3 = GND plane in green

I am wondering which via fence configuration is most efficient in reducing EMI emissions? Adding via fences on the edge of the copper pour as well as between the differential pairs (i.e. the top sketch in the attached picture) or via fences only on the two outer edges of the copper pour along the outer traces (i.e. bottom sketch in the attached picture)?

Thank you

[T3sl4co1l]

Do you know the radiation is coming from the board area itself, and not the connectors, say?

Tim

[Bud]

You may want to consider via stitching around the board perimeter. I am just parroting what i learned from PCB RF experts that a PCB may emmit through its edges because it represent a waveguide with the aperture of the PCB thickness. To mitigate that one could stich the PCB ground planes around the perimeter with via spacing of  minimum 1/10 of such waveguide wavelength. I will let you do the math.

[ricko_uk]

Thank you Tim and Bud,
for some reason have not been receiving post notifications so only seeing your replies now.

Tim,
no idea if it is the board or the connectors. How can I find out?

Thank you

[Smokey]

near field probes + spectrum analyzer. 

[mick_lee]

Firstly, a via fence is generally used to reduce crosstalk between conductors more than contain emissions.
Emissions are generally induced by abrupt changes in transmission line impedance - sharp corners and other transitions disturb the field pattern (reactive discontinuities) which can radiate. Mismatched impedances and unterminated lines are also best avoided.  Where possible - launch in the plane of the board (edge launch) - avoid right angled connectors if you can.  Anyway, that said - back to via fences...

The rule of thumb is space them at no more than 1/10 of a wavelength at the highest frequency of interest to approximate an 'E' wall.  Don't forget that the wavelength in the dielectric material (buried stripline) is reduced by sqrt(Er) and sqrt(Ereff) for micro striplines on the outside layer.  If you are carrying digital signals (squarewave) they will have a high harmonic content, so you will need to contain frequencies that are several multiples of your signal fundamental (I would suggest at least 10 times).  So if your fundamental is 100MHz - you would need to design for 1GHz.  free space wave length at 1 GHz is 300mm - so 30mm spacing in free space - reduce by sqrt of dielectric constant (around 4.5 for standard FR4) - lets just halve is so 15mm is adequate - although you would probably want to make them a bit closer.
At 10GHz the spacing needs to be 1.5mm, at 30GHz 0.5mm etc,etc...
Hope that helps

[tszaboo]

OK, so it passed the certification. Why are you changing it? Do you know if your changes will improve the situation, or make it worse?
If it will improve it, why would you improve it? It passed, doesn't matter if it was 1dB below the limit or 20, it's a pass/fail criteria.

[ricko_uk]

Thank you all,

@ smokey, I have near field probles and spectrum analyser but did not see any difference between various areas of the PCB and next to the connectors. Any additional suggestion?

@mick_lee useful explanation!

@tszaboo, because it passed the test at Intertek UK but not in the certification lab in the far east. The emission certification protocol allows for several dB variation between labs so I assume that's why it did not pass over there but it did over here.

Thank you as always

[Smokey]

...
because it passed the test at Intertek UK but not in the certification lab in the far east
....

That's a first.  Did you not bring enough cash that day?

[redkitedesign]

no idea if it is the board or the connectors. How can I find out?

I've designed probably a hundred boards with high speed (up to 40G) signals. Most of them have been EMC-tested, and at least half of them passed on the first try.

I've never used via-fencing for EMC reasons. I do have seen problems with connectors on multiple boards (including multiple low-speed connector openings colluding to create a multi-aperture antenna for backplane signals. And thus creating a powerfull beam at a certain angle from the front. That sucks.)

So without further information, I would guess your connectors are the major source of emitted field, not the PCB edges.