It certainly can be done (so long as the vias are properly overplated, see IPC-6012). There are a lot of factors besides layout that can contribute to tombstoning (component placement, reflow profile, paste print quality, component height, etc), and if all of those are done well you can often get away with murder on the layout. If you're working with a good CM which will profile the boards before real assembly (i.e. not JLCPCB), I wouldn't worry much. Otherwise, I would at least avoid vias directly to large inner planes, and would try to "balance" things by having VIP on both leads. I'm assuming you're at least using blind vias, otherwise you might have trouble routing these traces...