Ideas for a logic tester input stage?

[markhen]

Hi - what would you suggest for designs to satisfy this logic tester input stage requirement?

- Input signal: 3V to 5V logic signals up to something like 70-100MHz while preserving duty cycle.
- Output signal: 3.3V CMOS logic levels
- Input impedance >= 1Mohm
- Overvoltage tolerant on input +24V DC to -24V DC (must remain high impedance during overvoltage)
- Low cost (ideally less than USD $2 for all components at 100 qty)
- Low power (less than 5mA from a single 3.3V supply - less is better)
- SMT only (small PCB area, discrete and/or IC ok)

I've breadboarded a couple of simple single stage MOSFET circuits (common source, common drain) that almost meet the requirement, but I don't have a lot of experience in this realm, I'm sure others have better ideas!

[David Hess]

An inexpensive fast CMOS comparator like the TC75S56FUTE85LF, TC75S58FTE85LF, or TC75W57FKTE85LF could be used.  A resistive divider at the input provides a 1 megohm input and increases the input voltage range.

[SpacedCowboy]

An inexpensive fast CMOS comparator like the TC75S56FUTE85LF, TC75S58FTE85LF, or TC75W57FKTE85LF could be used.  A resistive divider at the input provides a 1 megohm input and increases the input voltage range.

The power:frequency curve doesn’t look too friendly for ~100 MHz on those. A pity because I’d like to find something that protected inputs at similar (or even higher) clock rates.

[Terry Bites]

Strays the undoing of us all.

You want a measuring end pcb with the recievers or comparators on- ie only a few cm of probe wire.
I'd be thinking of using something like SN75LVDS31 on the head end, diff lines to a SN75LVDS32's at the uP end.
As a bonus you get nosie isolation from the TUT- thingy under test and vice versa.
Local 3.3 voltage regs and heavy decoupling on the head end as well.

[SiliconWizard]

The big point here is "preserving duty cycle".
If your input range is 3V to 5V, I would consider 3V-powered, 5V-tolerant buffer gates, rather than a comparator-based solution.

[SpacedCowboy]

Digital logic is pretty forgiving, though - my Saleae can happily sample at 500MS/s and it just has a 6" flying lead from a 0.1" pin-header to a standard spring-loaded gripper - now admittedly they provide a separate ground for each input, but in practice I've never actually used them that way (and they all connect back to the same ground anyway, as far as I can tell, so I'm not really seeing the benefit of multiple leads). I can certainly sample at the max rate on 4 channels and only use one ground lead attached without problems.

 

[David Hess]

An inexpensive fast CMOS comparator like the TC75S56FUTE85LF, TC75S58FTE85LF, or TC75W57FKTE85LF could be used.  A resistive divider at the input provides a 1 megohm input and increases the input voltage range.

The power:frequency curve doesn’t look too friendly for ~100 MHz on those. A pity because I’d like to find something that protected inputs at similar (or even higher) clock rates.

Because of their requirements, comparators do not generally have high impedance inputs, so if you want a high impedance input then the input signal needs to be buffered by a linear stage.  The parts I listed are an exception which might be suitable up to 100 MHz in a low cost application.

Otherwise pick your favorite linear stage as an impedance buffer, like a pair of RF JFETs, followed by a more conventional fast comparator with low impedance inputs to get the performance that you require.

[SpacedCowboy]

The big point here is "preserving duty cycle".
If your input range is 3V to 5V, I would consider 3V-powered, 5V-tolerant buffer gates, rather than a comparator-based solution.

I'm considering a couple of things myself:

• The boards that will do the actual sampling are going to be plug-in boards with a relatively cheap ($6.50) FPGA on, so I might just leave them totally bare (with maybe a resistor to limit current into the FPGA). That way there's nothing between the signal and the sampler, and if you screw up and feed 5v in and blow the chip on the {1.2,1.8,3.3}-volt daughterboard, well, just get another  .
• There are several fairly high-spec level-converters (eg: 74LVC1T45), but you have to be careful with specs - translating from 5v to 3.3v it's "only" 210MHz, and I would really like 400MHz. For large numbers of input/output they don't come cheap, leading to the "you can get it if you want, but you have to pay for the extra 5v-tolerant board" approach, and it doesn't work at as high a frequency.

200MHz sounds fine for OP (if the +5v is an acceptable limit) but I'm still undecided - and I'm not really finding too many options "off the shelf" for a 400MHz clock rate from 5v to 3.3v

[free_electron]

what logic levels ? there are many different logic families. they all have different logic levels. to make a device that can flag a correct high and a correct low you need TWO comparators.
Use two dacs. one to set the low level, one to set the high level. an exor gate at the output of the comparators recreates the signal. ( there is a deadband between the two levels that needs to be filtered out.)

Then you have the complete flexibility to set high and low level thresholds to the specification of the logic family.

[markhen]

Thanks to all for thoughts and ideas. Some feedback/answers:

@David Hess: thanks, I like the idea of a comparator or FET(s) followed by a Schmitt buffer (assuming I can get a comparator that's fast enough and low cost)

@Terry Bites: agree, fortunately I can keep everything close/short to the DUT, while trying to reduce strays as much as possible. I think would have to clamp inputs on SN75LVDS31 (compromising the high impedance req.?)

@SpacedCowboy: Salae style inputs would work fine for me except for the high input impedance req outside of normal logic levels

@free_electron: main test parameter of interest is pulse timing (high and low times), input signals can be assumed to be 3.3V CMOS or 5V TTL (so Vil = 0.8V and Vih = 2.0V), so no need for DAC-adjustable levels

[Terry Bites]

I was thinking about this again- I forgot that it needs to accomodate 3.3 and 5V. 
What about using a buffer and changing is Vdd to suit your range. eg SN74AC244/ SN74AHC16240 / SN74AHC16244/ SN74AHC16540 and others. Add a 3k in series with the input to limit the protection clamp current.

I assume you mean 2$ per chanel!

[spostma]

I would use dual supply level translating buffers like 74AXP1T34, NLSV8T244, 74LVX3245 or 74LVX14

[Marco]

UHS logic seems fast enough and can do 5v, series resistor with parallel capacitor for input protection?

[SiliconWizard]

So you didn't like the idea of 5V-tolerant buffers?

Of course that won't be enough as far as protection is concerned, you'll still need proper protection as a front-end to be able to withstand +/- 24V.

[Marco]

They have diodes to the rails already, probably just a couple diodes in series for the positive rail in the case of 5V tolerant ones on 3.3V supply. A series resistor to limit DC current with a parallel capacitor to speed it up should be enough. The 100 MHz toggle rate without too much differential delay of the flanks is the biggest issue, the buffer needs to be really fast. So UHS, fast and overvoltage tolerant inputs.

PS. actually I think UHS have a TVS inside to clamp the input, not a diode string to positive rail, they say 7V input tolerance regardless of supply.

[markhen]

Since logic inputs have the clamps (and/or need clamps), running straight into a logic gate/buffer can't meet the input impedance >1Mohm requirement over the +/- 24V range

[Marco]

1 Meg//100p in series with the input.

PS. if the leakage current is low enough any way.

[markhen]

Marco - thanks, that will take care of the overvoltage protection, but I think the buffer input capacitance (combined with the 1Mohm) will not meet the bandwidth or duty cycle requirements?

[Marco]

I meant 1 mega Ohm parallel with 100 pico Farad. For high frequency signals the 100 pF forms a divider with the ~1 pF input capacitance of the logic gate.