Voltage-controlled resistor for potentiostat?

[bartd]

Hi all,

First post. I'm a hobbyist and teaching myself so please go easy on me.

We use potentiostats at work and the need has arisen for a current booster. Having successfully built a number of other electronic devices for work over the years I thought I'd give it a go myself.

The potentiostat in question cuts out at about 30 mA, the booster should be able to boost that 100x, i.e. up to about 3 A.

Its operation should be as follows, with reference to the figure below. The potentiostat puts out a voltage between out_1 and out_2. This voltage is copied exactly but "oomph" is added (buffer). The "copied" voltage is put across the sample which draws current (I_out, up to +/- 3 A). This current is measured, scaled down 100x (up to +/- 30 mA), and coded as a voltage (V_ctrl, 20 mV/mA). V_ctrl then drives the current scaler/mirror which makes the scaled-down current flow between the potentiostat electrodes.



What I know about the potentiostat: its output (between out_1 and out_2) is max +/- 10 V, each of out_1 and out_1 is max +/- 10 V from ground, and we only use it at very low frequencies (mostly fractions of a Hz) with triangle ramps. Unfortunately I don't know whether one of out_1 or out_2 is always at ground or not. It probably is, and a quick measurement confirmed that, but I cannot assume that this will always be the case for all experiments that the potentiostat is capable of, so I'm designing for a floating output (e.g. 10 V between out_1 and out_2 could be -5 V and +5 V with respect to ground).

I've got the voltage buffer part (referencing to ground, class-AB-type amplifier stage with feedback, current limiting etc).

I'm working on the current scaler/mirror now.

The first idea was to use an n-channel JFET as the "resistor", controlled by feedback from a current sense resistor as below. Q1 has to be a JFET because a BJT would work only one way and MOSFETs have a body diode which would ruin the plan when V_12 (voltage between out_1 and out_2) polarity inverts. R3 is 2 ohms (so 2 mV/mA). This is scaled back up to 20 mV/mA by instrumentation amplifier U2 (maybe INA101 or INA128). U3 and U4 are active rectifiers (based on opamps etc). The absolute value of U2 output is compared with the absolute value of V_ctrl by opamp U1 and its output drives the JFET's gate. Trimmer R2 is for calibrating away the tolerance of R3 and U2's gain error.



The biggest problem with this circuit that I can see (let me know if this isn't THE biggest one) is that I can't find any JFETs that would pass lots of current at low V_DS (e.g. 30 mA at 0.2 V_DS) and at the same time have small enough pinch-off voltage to fit between -10 V (lowest possible out_1 or out_2) and the -15 V rail to make sure it can be completely off. I thought perhaps something like the 2N4392 or the dual IFN146 might do, but even these have marginal saturation current specs and these are at 20 or 10 V_DS: what happens at 0.1 V_DS? I could parallel a few of them but how many to ensure 30 mA capability and how many would I need to still give 30 mA at very low V_DS? Plus they're not exactly cheap. I realise the need for the full 30 mA at a very low V_12 is unlikely to happen in practice but I don't want to impose this artificial limitation. Also, if the target current cannot be reached (because of low V_DS) with a reasonable V_GS, U1 will eventually forward-bias Q1's gate and inject current into out_1 or out_2. R1 can reduce this to something small but I don't know how the potentiostat would react to this and I don't want to risk anything that might break it (they're expensive). Also, all the active rectifiers add more opamp offsets/trimming/headaches and it just doesn't seem very elegant.

To overcome the problem of insufficient current at low V_DS I figured I'd try actively driving the potentiostat outputs, as below. There is no rectification of V_ctrl this time. Note that V_ctrl is always the same polarity as V_12 (at least under normal operation with passive samples) thus for a positive V_ctrl out_1 is more positive than out_2 and vice versa.

For the upper leg, a positive V_ctrl will cause opamp U5A to drive the p-channel MOSFET Q3 of the push-pull pair and thus cause current to flow FROM out_1 through current sense resistor R8. R8 is 10 ohms (10 mV/mA) so instrumentation amp U6 has gain of 2 and will balance the input to U5A when the required current is flowing. R4/R5 are for trimming away tolerance of current sense resistor and U6 gain error. This is also the reason for using 10 ohms for R8 (rather than 20 ohms) and having U6 with gain of 2: instrumentation amps can't have a gain of less than 1 as far as I know so adjustment wouldn't be possible if it had to go lower. A negative V_ctrl (which, in normal operation, implies that out_1 is also more negative than out_2) will drive MOSFET Q2 and cause current to flow INTO out_1 through current sense resistor R8.

For the lower leg everything is the same but inverted (so that when current flows FROM out_1, it flows INTO out_2, and vice versa).



What I like about this circuit is its symmetry. There's also the capability to drive active loads, i.e. something that would cause current to flow against the direction implied by V_12, although I'm not sure how/if the potentiostat would handle that and if that's allowed.

What I like less is that both legs are separate and so in principle (if not properly trimmed) quite different currents could flow from/into the two potentiostat electrodes. Not sure how the potentiostat would handle this and I don't want to break it. It also seems inelegant to have to trim both legs separately (R5 and R7). What I also don't like is that current is "injected artificially" into/out of the potentiostat rather than just controlling the current that the potentiostat "naturally" wants to circulate. Just seems like more potential for something going wrong and frying the potentiostat. Is there a more elegant/better way of doing this?

Everything is on paper so far, not breadboarded anything yet, although I'm at the point where I'm about to start ordering in components and see how things work. I realise what I'm looking for is essentially a "voltage-controlled resistor" and some googling throws up "transconductance amplifiers". Should I be looking into this? I would appreciate any thoughts on my attempted designs. But please go easy on me!

Thanks,
Bart

[moffy]

Use LTSpice to model your ideas first. That will answer a lot of questions.

[Terry Bites]

A booster stage can give rise to stability problems so some sort of compensation is required. A simple integrator network and gate resistor will prevent this. www.electronicsweekly.com/blogs/engineer-in-wonderland/current-sink-stability-2015-10/

If the outputs are not sinking/ sourcing from ground or other fixed reference then you may get an operating point problem. The current is defined as expected, but the source and sink terminals may not be properly centred on the reference. A simulation may give you a misleading result by assuming perfect symmetry.

[bartd]

A booster stage can give rise to stability problems so some sort of compensation is required. A simple integrator network and gate resistor will prevent this. www.electronicsweekly.com/blogs/engineer-in-wonderland/current-sink-stability-2015-10/

Thanks for this, I had a suspicion there should probably be some capacitors in there. Although I hoped I could get away without since the booster will only ever be used at very low frequencies (typically fractions of a Hz). I'll put in a high-pass filter into the feedback path.

I have not used LTSpice until now. Had a look at a tutorial earlier, should probably start getting into it. One potential problem I can see is that I've mixed AD and TI parts in my design. Are there models for TI components that work with LTSpice?

If the outputs are not sinking/ sourcing from ground or other fixed reference then you may get an operating point problem. The current is defined as expected, but the source and sink terminals may not be properly centred on the reference. A simulation may give you a misleading result by assuming perfect symmetry.

I do not fully follow what's what in the schematic you attached. I assume G1 and G2 are the upper and lower legs of my schematic and V3 and V4 are the potentiostat terminals? In any case, I'm pretty certain the potentiostat outputs are tied to some fixed reference (it has a reference electrode which we always tie to the counter electrode). It also has a ground connection, which I assume is the potentiostat's circuit ground which I can tie to the booster's ground so I'm hopeful the issue you described will not arise.

Just spent close to £100 (work money) on parts to start breadboarding things. Should be interesting...