Voltage Regulator Power Good Signal

[veryevil]

Hi, Im looking to use a MCP1825 in a project im working on. This LDO Regulator has a POWER GOOD signal. I thought it would be a nice feature to use this output to delay the switch on of the board.

However I have not found a single example of someone doing this and I am not sure why?

My first thought would be to use the PWRGD signal to switch on a MOSFET which would go across Vout and the load so the load would not receive power until PWRGD went high, would this work and how would I design the FET part as I am not overly familier with FETS?

Vin = 5v
Vout = 3.3v
Imax = 500mA

Thanks
Steven

[ivan747]

Use a P channel MOSFET with a 10K resistor going to the output of the voltage regulator and going to the transistor's gate. Connect the transistor's gate to the Power good signal. Connect the source (the pin with an arrow pointing outwards) to the output of the voltage regulator. The drain pin will give 3.3V when power is good.

Remember the pinout (this is NOT the circuit I am talking about):


A more efficient way of turning digital circuits off with a power good signal is to attach all the reset lines to the power good signal and a pull-up.

[Balaur]

The Power Good signals are not intended to be used to switch ON/OFF the power rail.

A soft start such as indicated in figures 2-25 and 2-26 is actually better for nicely starting up the attached devices.

As ivan747 said, the Power Good signal can drive reset inputs to allow the circuits to reliably start at the correct state when the power is stable.

Another use is for chaining the start-up of multiple regulators (i.e Power Good of the first regulator to an Enable/Shutdown of the following one) in order to ensure the correct sequence of the power domains for devices (FPGAs, MCUs, CPUs, etc) that are sensitive to this aspect.

Cheers,
Dan

[ivan747]

Another use is for chaining the start-up of multiple regulators (i.e Power Good of the first regulator to an Enable/Shutdown of the following one) in order to ensure the correct sequence of the power domains for devices (FPGAs, MCUs, CPUs, etc) that are sensitive to this aspect.

Cheers,
Dan

I never though of that use. I guess you can also add a simple R-C delay and a schmitt trigger (unless the Enable pin has one) to produce a time delay if required.