Minimum trace width is 6mil, minimum spacing is 6mil, except for power, which is 10mil. Power trace width varies between 6mil and 50mil, based on maximum calculated current on the trace plus 10%.
You might want to check out your PCB manufacturers abilities. Alternatively you have heaps of room, why make life difficult for your manufacturer/yourself by using 6mil when you could readily use 10mil if you're still imperial or 0.2mm if you like metric. Or better yet 0.3mm where you can. If tracks are too thick to go between header pins (like the Display header) feel free to use the bottom layer, it won't hurt anything.
I'm also taking a closer look at your decoupling caps placement (and general component placement) on the main IC, this area could use a bit of work:
You have C9, C10, C11 and C12 all connected really close to each other, but they go to pins 3, 7 and 48 on your IC. Each 100nF cap should be located close to each of those pins as they are to provide high frequency current. Same goes for C6 on VCCA (which should also have a 100nF in parallel). I suggest you rework all the components around the main IC.
-First put the 4x100nF decoupling capacitors close to their relevant pins. Also put C5 and C7 near their pins. These should be nonpolar MLCC type (you've drawn them as polar).
-Secondly put Y1 and Y2 near the IC also (coincidentally, are you sure that's the correct pinout of Y2, I've usually seen them as the diagonal pins are the crystal, and does it need capacitors?).
-Thirdly think about where your pullups and pulldowns will go. Although they arnt critical, you should be able to get them neatly around your IC.
-Fourth reconsider decoupling capacitor placement for other ICs. E.g. your mini54 (which doesn't have a silk screen designator) has no local decoupling - put in another 100nF cap next to its power pin. Same deal for RM24EP, needs a 100nF cap. Same deal for U2, needs a 100nF cap.
-U3 will probably have some specific capacitor requirements in its datasheet. "
The PA supply should preferably be bypassed with a 10 to 100uF capacitor to smooth out the current spikes drawn by the Wi-Fi power amplifier. External high frequency bypassing is not needed, the module contains the needed supply filtering capacitors."
-The general routing to the other ICs looks pretty good though (once you thicken the traces a bit).
The whole top layer GND and via stiching is really unimportant for a board of this not-so-complexity (
I know others here will disagree). Especially compared to IC decoupling capacitor placement. I don't think you need to be so over the top about not cutting into the bottom layer ground plane. You don't need the 3.3V line to come back up to the top layer then drop back down to the bottom layer.
Forgive my ignorance, but what's the purpose of the circuit Q1, Z1 and R1? Some kind of backfeed protection?
A more general comment on your schematic - you should consider putting it on 2 pages with a left to right flow. I.e. your voltage regulation circuitry appears to be squeezed in, which makes it very hard to follow and leaves you open to simple mistakes. Same applies to your headers, which are everywhere on your schematic and provide no context to where they go. I'd also frown upon placing ICs vertically (RM24EP).
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